2 * Aeronix Zipit Z2 configuration file
4 * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
6 * SPDX-License-Identifier: GPL-2.0+
13 * High Level Board Configuration Options
15 #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
16 #define CONFIG_SYS_TEXT_BASE 0x0
18 #undef CONFIG_BOARD_LATE_INIT
19 #undef CONFIG_SKIP_LOWLEVEL_INIT
20 #define CONFIG_PREBOOT
23 * Environment settings
25 #define CONFIG_ENV_OVERWRITE
26 #define CONFIG_ENV_IS_IN_FLASH 1
27 #define CONFIG_ENV_ADDR 0x40000
28 #define CONFIG_ENV_SIZE 0x10000
30 #define CONFIG_SYS_DCACHE_OFF
32 #define CONFIG_SYS_MALLOC_LEN (128*1024)
33 #define CONFIG_ARCH_CPU_INIT
35 #define CONFIG_BOOTCOMMAND \
36 "if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\
38 "source 0xa0000000; " \
42 #define CONFIG_BOOTARGS \
43 "console=tty0 console=ttyS2,115200 fbcon=rotate:3"
44 #define CONFIG_TIMESTAMP
45 #define CONFIG_BOOTDELAY 2 /* Autoboot delay */
46 #define CONFIG_CMDLINE_TAG
47 #define CONFIG_SETUP_MEMORY_TAGS
48 #define CONFIG_SYS_TEXT_BASE 0x0
49 #define CONFIG_LZMA /* LZMA compression support */
50 #define CONFIG_OF_LIBFDT
53 * Serial Console Configuration
54 * STUART - the lower serial port on Colibri board
56 #define CONFIG_PXA_SERIAL
57 #define CONFIG_STUART 1
58 #define CONFIG_CONS_INDEX 2
59 #define CONFIG_BAUDRATE 115200
62 * Bootloader Components Configuration
64 #define CONFIG_CMD_ENV
65 #define CONFIG_CMD_MMC
66 #define CONFIG_CMD_SPI
67 #define CONFIG_CMD_USB
70 * MMC Card Configuration
74 #define CONFIG_GENERIC_MMC
75 #define CONFIG_PXA_MMC_GENERIC
76 #define CONFIG_SYS_MMC_BASE 0xF0000000
77 #define CONFIG_CMD_FAT
78 #define CONFIG_CMD_EXT2
79 #define CONFIG_DOS_PARTITION
86 #define CONFIG_SOFT_SPI
88 #define CONFIG_LCD_ROTATION
89 #define CONFIG_PXA_LCD
90 #define CONFIG_LMS283GF05
92 #define SPI_DELAY udelay(10)
93 #define SPI_SDA(val) zipitz2_spi_sda(val)
94 #define SPI_SCL(val) zipitz2_spi_scl(val)
95 #define SPI_READ zipitz2_spi_read()
97 void zipitz2_spi_sda(int);
98 void zipitz2_spi_scl(int);
99 unsigned char zipitz2_spi_read(void);
104 * HUSH Shell Configuration
106 #define CONFIG_SYS_HUSH_PARSER 1
108 #define CONFIG_SYS_LONGHELP /* undef to save memory */
109 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
110 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
111 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
112 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
113 #define CONFIG_SYS_DEVICE_NULLDEV 1
116 * Clock Configuration
118 #define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
123 #define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */
124 #define PHYS_SRAM_SIZE 0x00040000 /* 256k */
129 #define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */
130 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
131 #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
133 #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
134 #define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */
136 #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
137 #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
139 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
141 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
142 #define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048)
147 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
148 #define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
149 #define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */
150 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
152 #define CONFIG_SYS_FLASH_CFI
153 #define CONFIG_FLASH_CFI_DRIVER 1
154 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
156 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
157 #define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
159 #define CONFIG_SYS_MAX_FLASH_BANKS 1
160 #define CONFIG_SYS_MAX_FLASH_SECT 256
162 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
164 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000
165 #define CONFIG_SYS_FLASH_WRITE_TOUT 240000
166 #define CONFIG_SYS_FLASH_LOCK_TOUT 240000
167 #define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000
168 #define CONFIG_SYS_FLASH_PROTECTION
173 #define CONFIG_SYS_GAFR0_L_VAL 0x02000140
174 #define CONFIG_SYS_GAFR0_U_VAL 0x59188000
175 #define CONFIG_SYS_GAFR1_L_VAL 0x63900002
176 #define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950
177 #define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa
178 #define CONFIG_SYS_GAFR2_U_VAL 0x29000308
179 #define CONFIG_SYS_GAFR3_L_VAL 0x54000000
180 #define CONFIG_SYS_GAFR3_U_VAL 0x000000d5
181 #define CONFIG_SYS_GPCR0_VAL 0x00000000
182 #define CONFIG_SYS_GPCR1_VAL 0x00000020
183 #define CONFIG_SYS_GPCR2_VAL 0x00000000
184 #define CONFIG_SYS_GPCR3_VAL 0x00000000
185 #define CONFIG_SYS_GPDR0_VAL 0xdafcee00
186 #define CONFIG_SYS_GPDR1_VAL 0xffa3aaab
187 #define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff
188 #define CONFIG_SYS_GPDR3_VAL 0x001b1f8a
189 #define CONFIG_SYS_GPSR0_VAL 0x06080400
190 #define CONFIG_SYS_GPSR1_VAL 0x007f0000
191 #define CONFIG_SYS_GPSR2_VAL 0x032a0000
192 #define CONFIG_SYS_GPSR3_VAL 0x00000180
194 #define CONFIG_SYS_PSSR_VAL 0x30
199 #define CONFIG_SYS_CKEN 0x00511220
200 #define CONFIG_SYS_CCCR 0x00000190
205 #define CONFIG_SYS_MSC0_VAL 0x2ffc38f8
206 #define CONFIG_SYS_MSC1_VAL 0x0000ccd1
207 #define CONFIG_SYS_MSC2_VAL 0x0000b884
208 #define CONFIG_SYS_MDCNFG_VAL 0x08000ba9
209 #define CONFIG_SYS_MDREFR_VAL 0x2011a01e
210 #define CONFIG_SYS_MDMRS_VAL 0x00000000
211 #define CONFIG_SYS_FLYCNFG_VAL 0x00010001
212 #define CONFIG_SYS_SXCNFG_VAL 0x40044004
215 * PCMCIA and CF Interfaces
217 #define CONFIG_SYS_MECR_VAL 0x00000001
218 #define CONFIG_SYS_MCMEM0_VAL 0x00014307
219 #define CONFIG_SYS_MCMEM1_VAL 0x00014307
220 #define CONFIG_SYS_MCATT0_VAL 0x0001c787
221 #define CONFIG_SYS_MCATT1_VAL 0x0001c787
222 #define CONFIG_SYS_MCIO0_VAL 0x0001430f
223 #define CONFIG_SYS_MCIO1_VAL 0x0001430f
225 #include "pxa-common.h"
227 #endif /* __CONFIG_H */