2 * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 /************************************************************************
24 * 1 january 2005 Alain Saurel <asaurel@amcc.com>
25 * Adapted to current Das U-Boot source
26 ***********************************************************************/
27 /************************************************************************
28 * yucca.h - configuration for AMCC 440SPe Ref (yucca)
29 ***********************************************************************/
37 /*-----------------------------------------------------------------------
38 * High Level Configuration Options
39 *----------------------------------------------------------------------*/
40 #define CONFIG_4xx 1 /* ... PPC4xx family */
41 #define CONFIG_440 1 /* ... PPC440 family */
42 #define CONFIG_440SPE 1 /* Specifc SPe support */
43 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
44 #undef CFG_DRAM_TEST /* Disable-takes long time */
45 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
46 #define EXTCLK_33_33 33333333
47 #define EXTCLK_66_66 66666666
48 #define EXTCLK_50 50000000
49 #define EXTCLK_83 83333333
51 #define CONFIG_IBM_EMAC4_V4 1
52 #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
53 #undef CONFIG_SHOW_BOOT_PROGRESS
56 /*-----------------------------------------------------------------------
57 * Base addresses -- Note these are effective addresses where the
58 * actual resources get mapped (not physical addresses)
59 *----------------------------------------------------------------------*/
60 #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
61 #define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */
62 #define CFG_MONITOR_BASE 0xfffb0000 /* start of monitor */
63 #define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */
64 #define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */
66 #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
67 #define CFG_PCI_MEMBASE1 0x90000000 /* mapped pci memory */
68 #define CFG_PCI_MEMBASE2 0xa0000000 /* mapped pci memory */
69 #define CFG_PCI_MEMBASE3 0xb0000000 /* mapped pci memory */
71 #define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
72 #define CFG_PCI_TARGBASE 0x80000000 /*PCIaddr mapped to CFG_PCI_MEMBASE*/
74 /* #define CFG_PCI_BASE_IO 0xB8000000 */ /* internal PCI I-O */
75 /* #define CFG_PCI_BASE_REGS 0xBEC00000 */ /* internal PCI regs */
76 /* #define CFG_PCI_BASE_CYCLE 0xBED00000 */ /* internal PCI regs */
78 #define CFG_FPGA_BASE 0xe2000000 /* epld */
79 #define CFG_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */
81 /* #define CFG_NVRAM_BASE_ADDR 0x08000000 */
82 /*-----------------------------------------------------------------------
83 * Initial RAM & stack pointer (placed in internal SRAM)
84 *----------------------------------------------------------------------*/
85 #define CFG_TEMP_STACK_OCM 1
86 #define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
87 #define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
88 #define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
89 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
91 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
92 #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
93 #define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
95 #define CFG_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Mon */
96 #define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */
98 /*-----------------------------------------------------------------------
100 *----------------------------------------------------------------------*/
101 #define CONFIG_SERIAL_MULTI 1
102 #undef CONFIG_UART1_CONSOLE
104 #undef CONFIG_SERIAL_SOFTWARE_FIFO
105 #undef CFG_EXT_SERIAL_CLOCK
106 /* #define CFG_EXT_SERIAL_CLOCK (1843200 * 6) */ /* Ext clk @ 11.059 MHz */
108 #define CONFIG_BAUDRATE 115200
110 #define CFG_BAUDRATE_TABLE \
111 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
113 /*-----------------------------------------------------------------------
115 *----------------------------------------------------------------------*/
116 #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
117 #define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses */
118 #define IIC0_DIMM0_ADDR 0x53
119 #define IIC0_DIMM1_ADDR 0x52
121 /*-----------------------------------------------------------------------
123 *----------------------------------------------------------------------*/
124 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
125 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
126 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
127 #define CFG_I2C_SLAVE 0x7F
129 #define IIC0_BOOTPROM_ADDR 0x50
130 #define IIC0_ALT_BOOTPROM_ADDR 0x54
132 /* Don't probe these addrs */
133 #define CFG_I2C_NOPROBES {0x50, 0x52, 0x53, 0x54}
135 /* #if (CONFIG_COMMANDS & CFG_CMD_EEPROM) */
136 /* #define CFG_I2C_EEPROM_ADDR 0x50 */ /* I2C boot EEPROM */
137 #define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
140 /*-----------------------------------------------------------------------
142 *----------------------------------------------------------------------*/
143 /* #define CFG_NVRAM_SIZE (0x2000 - 8) */ /* NVRAM size(8k)- RTC regs */
145 #undef CFG_ENV_IS_IN_NVRAM /* ... not in NVRAM */
146 #define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
147 #undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
148 #define CONFIG_ENV_OVERWRITE 1
150 #define CONFIG_BOOTARGS "console=ttyS0,115200n8 root=/dev/nfs rw"
151 #define CONFIG_BOOTCOMMAND "bootm E7C00000" /* autoboot command */
152 #define CONFIG_BOOTDELAY -1 /* -1 to disable autoboot */
154 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
155 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
157 #define CONFIG_MII 1 /* MII PHY management */
158 #undef CONFIG_NET_MULTI
159 #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
160 #define CONFIG_HAS_ETH0
161 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
162 #define CONFIG_PHY_RESET_DELAY 1000
163 #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
164 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
165 #define CONFIG_NETMASK 255.255.0.0
166 #define CONFIG_IPADDR 192.168.80.10
167 #define CONFIG_ETHADDR 00:04:AC:01:CA:FE
168 #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
169 #define CONFIG_SERVERIP 192.168.1.1
171 #define CONFIG_EXTRA_ENV_SETTINGS \
175 "nfsargs=setenv bootargs root=/dev/nfs rw " \
176 "nfsroot=${serverip}:${rootpath}\0" \
177 "ramargs=setenv bootargs root=/dev/ram rw\0" \
178 "addip=setenv bootargs ${bootargs} " \
179 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
180 ":${hostname}:${netdev}:off panic=1\0" \
181 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
182 "flash_nfs=run nfsargs addip addtty;" \
183 "bootm ${kernel_addr}\0" \
184 "flash_self=run ramargs addip addtty;" \
185 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
186 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
188 "rootpath=/opt/eldk-4.0/ppc_4xx\0" \
189 "bootfile=yucca/uImage\0" \
190 "kernel_addr=E7F10000\0" \
191 "ramdisk_addr=E7F20000\0" \
192 "load=tftp 100000 yuca/u-boot.bin\0" \
193 "update=protect off 2:4-7;era 2:4-7;" \
194 "cp.b ${fileaddr} FFFB0000 ${filesize};" \
195 "setenv filesize;saveenv\0" \
196 "upd=run load;run update\0" \
199 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
211 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
212 #include <cmd_confdefs.h>
214 #undef CONFIG_WATCHDOG /* watchdog disabled */
217 * Miscellaneous configurable options
219 #define CFG_LONGHELP /* undef to save memory */
220 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
222 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
223 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
225 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
227 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
228 #define CFG_MAXARGS 16 /* max number of command args */
229 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
231 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
232 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
234 #define CFG_LOAD_ADDR 0x100000 /* default load address */
235 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
237 #define CFG_HZ 1 /* decrementer freq: 1 ms ticks */
239 /*-----------------------------------------------------------------------
241 *----------------------------------------------------------------------*/
242 #define CFG_MAX_FLASH_BANKS 3 /* number of banks */
243 #define CFG_MAX_FLASH_SECT 256 /* sectors per device */
245 #undef CFG_FLASH_CHECKSUM
246 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
247 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
249 #define CFG_FLASH_ADDR0 0x5555
250 #define CFG_FLASH_ADDR1 0x2aaa
251 #define CFG_FLASH_WORD_SIZE unsigned char
253 #define CFG_FLASH_2ND_16BIT_DEV 1 /* evb440SPe has 8 and 16bit device */
254 #define CFG_FLASH_2ND_ADDR 0xe7c00000 /* evb440SPe has 8 and 16bit device*/
256 #ifdef CFG_ENV_IS_IN_FLASH
257 #define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
258 #define CFG_ENV_ADDR 0xfffa0000
259 /* #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) */
260 #define CFG_ENV_SIZE 0x10000 /* Size of Environment vars */
261 #endif /* CFG_ENV_IS_IN_FLASH */
262 /*-----------------------------------------------------------------------
264 *-----------------------------------------------------------------------
267 #define CONFIG_PCI /* include pci support */
268 #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
269 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
270 #undef CONFIG_PCI_CONFIG_HOST_BRIDGE
272 /* Board-specific PCI */
273 #define CFG_PCI_PRE_INIT 1 /* enable board pci_pre_init() */
274 #define CFG_PCI_TARGET_INIT /* let board init pci target */
275 #undef CFG_PCI_MASTER_INIT
277 #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
278 #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
279 /* #define CFG_PCI_SUBSYS_ID CFG_PCI_SUBSYS_DEVICEID */
282 * NETWORK Support (PCI):
284 /* Support for Intel 82557/82559/82559ER chips. */
285 #define CONFIG_EEPRO100
287 * For booting Linux, the board info and command line data
288 * have to be in the first 8 MB of memory, since this is
289 * the maximum mapped by the Linux kernel during initialization.
291 #define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/
292 /*-----------------------------------------------------------------------
293 * Cache Configuration
295 #define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
296 #define CFG_CACHELINE_SIZE 32 /* ... */
297 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
298 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
302 * Internal Definitions
306 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
307 #define BOOTFLAG_WARM 0x02 /* Software reboot */
309 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
310 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
311 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
314 /* FB Divisor selection */
315 #define FPGA_FB_DIV_6 6
316 #define FPGA_FB_DIV_10 10
317 #define FPGA_FB_DIV_12 12
318 #define FPGA_FB_DIV_20 20
320 /* VCO Divisor selection */
321 #define FPGA_VCO_DIV_4 4
322 #define FPGA_VCO_DIV_6 6
323 #define FPGA_VCO_DIV_8 8
324 #define FPGA_VCO_DIV_10 10
326 /*----------------------------------------------------------------------------+
327 | FPGA registers and bit definitions
328 +----------------------------------------------------------------------------*/
329 /* PowerPC 440SPe Board FPGA is reached with physical address 0x1 E2000000. */
330 /* TLB initialization makes it correspond to logical address 0xE2000000. */
331 /* => Done init_chip.s in bootlib */
332 #define FPGA_REG_BASE_ADDR 0xE2000000
333 #define FPGA_GPIO_BASE_ADDR 0xE2010000
334 #define FPGA_INT_BASE_ADDR 0xE2020000
336 /*----------------------------------------------------------------------------+
338 +----------------------------------------------------------------------------*/
339 #define PPC440SPE_DISPLAY FPGA_REG_BASE_ADDR
341 #define PPC440SPE_DISPLAY_D8 (FPGA_REG_BASE_ADDR+0x06)
342 #define PPC440SPE_DISPLAY_D4 (FPGA_REG_BASE_ADDR+0x04)
343 #define PPC440SPE_DISPLAY_D2 (FPGA_REG_BASE_ADDR+0x02)
344 #define PPC440SPE_DISPLAY_D1 (FPGA_REG_BASE_ADDR+0x00)
345 /*define WRITE_DISPLAY_DIGIT(n) IOREG8(FPGA_REG_BASE_ADDR + (2*n))*/
346 /*#define IOREG8(addr) *((volatile unsigned char *)(addr))*/
348 /*----------------------------------------------------------------------------+
349 | ethernet/reset/boot Register 1
350 +----------------------------------------------------------------------------*/
351 #define FPGA_REG10 (FPGA_REG_BASE_ADDR+0x10)
353 #define FPGA_REG10_10MHZ_ENABLE 0x8000
354 #define FPGA_REG10_100MHZ_ENABLE 0x4000
355 #define FPGA_REG10_GIGABIT_ENABLE 0x2000
356 #define FPGA_REG10_FULL_DUPLEX 0x1000 /* force Full Duplex*/
357 #define FPGA_REG10_RESET_ETH 0x0800
358 #define FPGA_REG10_AUTO_NEG_DIS 0x0400
359 #define FPGA_REG10_INTP_ETH 0x0200
361 #define FPGA_REG10_RESET_HISR 0x0080
362 #define FPGA_REG10_ENABLE_DISPLAY 0x0040
363 #define FPGA_REG10_RESET_SDRAM 0x0020
364 #define FPGA_REG10_OPER_BOOT 0x0010
365 #define FPGA_REG10_SRAM_BOOT 0x0008
366 #define FPGA_REG10_SMALL_BOOT 0x0004
367 #define FPGA_REG10_FORCE_COLA 0x0002
368 #define FPGA_REG10_COLA_MANUAL 0x0001
370 #define FPGA_REG10_SDRAM_ENABLE 0x0020
372 #define FPGA_REG10_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*from ocotea ?*/
373 #define FPGA_REG10_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*from ocotea ?*/
375 /*----------------------------------------------------------------------------+
377 +----------------------------------------------------------------------------*/
378 #define FPGA_REG12 (FPGA_REG_BASE_ADDR+0x12)
380 #define FPGA_REG12_EBC_CTL 0x8000
381 #define FPGA_REG12_UART1_CTS_RTS 0x4000
382 #define FPGA_REG12_UART0_RX_ENABLE 0x2000
383 #define FPGA_REG12_UART1_RX_ENABLE 0x1000
384 #define FPGA_REG12_UART2_RX_ENABLE 0x0800
385 #define FPGA_REG12_EBC_OUT_ENABLE 0x0400
386 #define FPGA_REG12_GPIO0_OUT_ENABLE 0x0200
387 #define FPGA_REG12_GPIO1_OUT_ENABLE 0x0100
388 #define FPGA_REG12_GPIO_SELECT 0x0010
389 #define FPGA_REG12_GPIO_CHREG 0x0008
390 #define FPGA_REG12_GPIO_CLK_CHREG 0x0004
391 #define FPGA_REG12_GPIO_OETRI 0x0002
392 #define FPGA_REG12_EBC_ERROR 0x0001
394 /*----------------------------------------------------------------------------+
396 +----------------------------------------------------------------------------*/
397 #define FPGA_REG16 (FPGA_REG_BASE_ADDR+0x16)
399 #define FPGA_REG16_PCI_CLK_CTL0 0x8000
400 #define FPGA_REG16_PCI_CLK_CTL1 0x4000
401 #define FPGA_REG16_PCI_CLK_CTL2 0x2000
402 #define FPGA_REG16_PCI_CLK_CTL3 0x1000
403 #define FPGA_REG16_PCI_CLK_CTL4 0x0800
404 #define FPGA_REG16_PCI_CLK_CTL5 0x0400
405 #define FPGA_REG16_PCI_CLK_CTL6 0x0200
406 #define FPGA_REG16_PCI_CLK_CTL7 0x0100
407 #define FPGA_REG16_PCI_CLK_CTL8 0x0080
408 #define FPGA_REG16_PCI_CLK_CTL9 0x0040
409 #define FPGA_REG16_PCI_EXT_ARB0 0x0020
410 #define FPGA_REG16_PCI_MODE_1 0x0010
411 #define FPGA_REG16_PCI_TARGET_MODE 0x0008
412 #define FPGA_REG16_PCI_INTP_MODE 0x0004
414 /* FB1 Divisor selection */
415 #define FPGA_REG16_FB2_DIV_MASK 0x1000
416 #define FPGA_REG16_FB2_DIV_LOW 0x0000
417 #define FPGA_REG16_FB2_DIV_HIGH 0x1000
418 /* FB2 Divisor selection */
419 /* S3 switch on Board */
420 #define FPGA_REG16_FB1_DIV_MASK 0x2000
421 #define FPGA_REG16_FB1_DIV_LOW 0x0000
422 #define FPGA_REG16_FB1_DIV_HIGH 0x2000
423 /* PCI0 Clock Selection */
424 /* S3 switch on Board */
425 #define FPGA_REG16_PCI0_CLK_MASK 0x0c00
426 #define FPGA_REG16_PCI0_CLK_33_33 0x0000
427 #define FPGA_REG16_PCI0_CLK_66_66 0x0800
428 #define FPGA_REG16_PCI0_CLK_100 0x0400
429 #define FPGA_REG16_PCI0_CLK_133_33 0x0c00
430 /* VCO Divisor selection */
431 /* S3 switch on Board */
432 #define FPGA_REG16_VCO_DIV_MASK 0xc000
433 #define FPGA_REG16_VCO_DIV_4 0x0000
434 #define FPGA_REG16_VCO_DIV_8 0x4000
435 #define FPGA_REG16_VCO_DIV_6 0x8000
436 #define FPGA_REG16_VCO_DIV_10 0xc000
437 /* Master Clock Selection */
438 /* S3, S4 switches on Board */
439 #define FPGA_REG16_MASTER_CLK_MASK 0x01c0
440 #define FPGA_REG16_MASTER_CLK_EXT 0x0000
441 #define FPGA_REG16_MASTER_CLK_66_66 0x0040
442 #define FPGA_REG16_MASTER_CLK_50 0x0080
443 #define FPGA_REG16_MASTER_CLK_33_33 0x00c0
444 #define FPGA_REG16_MASTER_CLK_25 0x0100
446 /*----------------------------------------------------------------------------+
448 +----------------------------------------------------------------------------*/
449 #define FPGA_REG18 (FPGA_REG_BASE_ADDR+0x18)
451 #define FPGA_REG18_PCI_PRSNT1 0x8000
452 #define FPGA_REG18_PCI_PRSNT2 0x4000
453 #define FPGA_REG18_PCI_INTA 0x2000
454 #define FPGA_REG18_PCI_SLOT0_INTP 0x1000
455 #define FPGA_REG18_PCI_SLOT1_INTP 0x0800
456 #define FPGA_REG18_PCI_SLOT2_INTP 0x0400
457 #define FPGA_REG18_PCI_SLOT3_INTP 0x0200
458 #define FPGA_REG18_PCI_PCI0_VC 0x0100
459 #define FPGA_REG18_PCI_PCI0_VTH1 0x0080
460 #define FPGA_REG18_PCI_PCI0_VTH2 0x0040
461 #define FPGA_REG18_PCI_PCI0_VTH3 0x0020
463 /*----------------------------------------------------------------------------+
465 +----------------------------------------------------------------------------*/
466 #define FPGA_REG1A (FPGA_REG_BASE_ADDR+0x1A)
468 #define FPGA_REG1A_PE0_GLED 0x8000
469 #define FPGA_REG1A_PE1_GLED 0x4000
470 #define FPGA_REG1A_PE2_GLED 0x2000
471 #define FPGA_REG1A_PE0_YLED 0x1000
472 #define FPGA_REG1A_PE1_YLED 0x0800
473 #define FPGA_REG1A_PE2_YLED 0x0400
474 #define FPGA_REG1A_PE0_PWRON 0x0200
475 #define FPGA_REG1A_PE1_PWRON 0x0100
476 #define FPGA_REG1A_PE2_PWRON 0x0080
477 #define FPGA_REG1A_PE0_REFCLK_ENABLE 0x0040
478 #define FPGA_REG1A_PE1_REFCLK_ENABLE 0x0020
479 #define FPGA_REG1A_PE2_REFCLK_ENABLE 0x0010
480 #define FPGA_REG1A_PE_SPREAD0 0x0008
481 #define FPGA_REG1A_PE_SPREAD1 0x0004
482 #define FPGA_REG1A_PE_SELSOURCE_0 0x0002
483 #define FPGA_REG1A_PE_SELSOURCE_1 0x0001
485 /*----------------------------------------------------------------------------+
487 +----------------------------------------------------------------------------*/
488 #define FPGA_REG1C (FPGA_REG_BASE_ADDR+0x1C)
490 #define FPGA_REG1C_PE0_ROOTPOINT 0x8000
491 #define FPGA_REG1C_PE1_ENDPOINT 0x4000
492 #define FPGA_REG1C_PE2_ENDPOINT 0x2000
493 #define FPGA_REG1C_PE0_PRSNT 0x1000
494 #define FPGA_REG1C_PE1_PRSNT 0x0800
495 #define FPGA_REG1C_PE2_PRSNT 0x0400
496 #define FPGA_REG1C_PE0_WAKE 0x0080
497 #define FPGA_REG1C_PE1_WAKE 0x0040
498 #define FPGA_REG1C_PE2_WAKE 0x0020
499 #define FPGA_REG1C_PE0_PERST 0x0010
500 #define FPGA_REG1C_PE1_PERST 0x0080
501 #define FPGA_REG1C_PE2_PERST 0x0040
503 /*----------------------------------------------------------------------------+
505 +----------------------------------------------------------------------------*/
506 #define PERIOD_133_33MHZ 7500 /* 7,5ns */
507 #define PERIOD_100_00MHZ 10000 /* 10ns */
508 #define PERIOD_83_33MHZ 12000 /* 12ns */
509 #define PERIOD_75_00MHZ 13333 /* 13,333ns */
510 #define PERIOD_66_66MHZ 15000 /* 15ns */
511 #define PERIOD_50_00MHZ 20000 /* 20ns */
512 #define PERIOD_33_33MHZ 30000 /* 30ns */
513 #define PERIOD_25_00MHZ 40000 /* 40ns */
515 /*---------------------------------------------------------------------------*/
517 #endif /* __CONFIG_H */