sunxi: Add support for using MII phy-s with the GMAC nic
[oweals/u-boot.git] / include / configs / yucca.h
1 /*
2  * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 /************************************************************************
8  * 1 january 2005       Alain Saurel <asaurel@amcc.com>
9  * Adapted to current Das U-Boot source
10  ***********************************************************************/
11 /************************************************************************
12  * yucca.h - configuration for AMCC 440SPe Ref (yucca)
13  ***********************************************************************/
14
15 #ifndef __CONFIG_H
16 #define __CONFIG_H
17
18 /*-----------------------------------------------------------------------
19  * High Level Configuration Options
20  *----------------------------------------------------------------------*/
21 #define CONFIG_440                      1       /* ... PPC440 family    */
22 #define CONFIG_440SPE                   1       /* Specifc SPe support  */
23 #define CONFIG_440SPE_REVA              1       /* Support old Rev A.   */
24 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init  */
25 #define CONFIG_SYS_CLK_FREQ     33333333        /* external freq to pll */
26 #define EXTCLK_33_33            33333333
27 #define EXTCLK_66_66            66666666
28 #define EXTCLK_50               50000000
29 #define EXTCLK_83               83333333
30
31 #define CONFIG_SYS_TEXT_BASE    0xfffb0000
32
33 /*
34  * Include common defines/options for all AMCC eval boards
35  */
36 #define CONFIG_HOSTNAME         yucca
37 #include "amcc-common.h"
38
39 #define CONFIG_MISC_INIT_F      1       /* Use misc_init_f()            */
40 #undef  CONFIG_SHOW_BOOT_PROGRESS
41 #undef  CONFIG_STRESS
42
43 /*-----------------------------------------------------------------------
44  * Base addresses -- Note these are effective addresses where the
45  * actual resources get mapped (not physical addresses)
46  *----------------------------------------------------------------------*/
47 #define CONFIG_SYS_FLASH_BASE           0xfff00000      /* start of FLASH       */
48 #define CONFIG_SYS_ISRAM_BASE           0x90000000      /* internal SRAM        */
49
50 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped PCI memory    */
51 #define CONFIG_SYS_PCI_BASE             0xd0000000      /* internal PCI regs    */
52 #define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
53
54 #define CONFIG_SYS_PCIE_MEMBASE 0xb0000000      /* mapped PCIe memory   */
55 #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000      /* smallest incr for PCIe port */
56 #define CONFIG_SYS_PCIE_BASE            0xe0000000      /* PCIe UTL regs */
57
58 #define CONFIG_SYS_PCIE0_CFGBASE        0xc0000000
59 #define CONFIG_SYS_PCIE1_CFGBASE        0xc1000000
60 #define CONFIG_SYS_PCIE2_CFGBASE        0xc2000000
61 #define CONFIG_SYS_PCIE0_XCFGBASE       0xc3000000
62 #define CONFIG_SYS_PCIE1_XCFGBASE       0xc3001000
63 #define CONFIG_SYS_PCIE2_XCFGBASE       0xc3002000
64
65 /* base address of inbound PCIe window */
66 #define CONFIG_SYS_PCIE_INBOUND_BASE    0x0000000400000000ULL
67
68 /* System RAM mapped to PCI space */
69 #define CONFIG_PCI_SYS_MEM_BUS  CONFIG_SYS_SDRAM_BASE
70 #define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
71 #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
72
73 #define CONFIG_SYS_FPGA_BASE            0xe2000000      /* epld                 */
74 #define CONFIG_SYS_OPER_FLASH           0xe7000000      /* SRAM - OPER Flash    */
75
76 /* #define CONFIG_SYS_NVRAM_BASE_ADDR 0x08000000 */
77 /*-----------------------------------------------------------------------
78  * Initial RAM & stack pointer (placed in internal SRAM)
79  *----------------------------------------------------------------------*/
80 #define CONFIG_SYS_TEMP_STACK_OCM       1
81 #define CONFIG_SYS_OCM_DATA_ADDR        CONFIG_SYS_ISRAM_BASE
82 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_ISRAM_BASE   /* Initial RAM address  */
83 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000          /* Size of used area in RAM */
84
85 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
86 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
87
88 /*-----------------------------------------------------------------------
89  * Serial Port
90  *----------------------------------------------------------------------*/
91 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
92
93 #undef CONFIG_SYS_EXT_SERIAL_CLOCK
94 /* #define CONFIG_SYS_EXT_SERIAL_CLOCK  (1843200 * 6) */ /* Ext clk @ 11.059 MHz */
95
96 /*-----------------------------------------------------------------------
97  * DDR SDRAM
98  *----------------------------------------------------------------------*/
99 #define CONFIG_SPD_EEPROM       1       /* Use SPD EEPROM for setup     */
100 #define SPD_EEPROM_ADDRESS      {0x53, 0x52}    /* SPD i2c spd addresses*/
101 #define CONFIG_DDR_ECC          1       /* with ECC support             */
102
103 /*-----------------------------------------------------------------------
104  * I2C
105  *----------------------------------------------------------------------*/
106 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
107
108 #define IIC0_BOOTPROM_ADDR      0x50
109 #define IIC0_ALT_BOOTPROM_ADDR  0x54
110
111 /* Don't probe these addrs */
112 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x50}, {0, 0x52}, {0, 0x53}, {0, 0x54} }
113
114 /* #if defined(CONFIG_CMD_EEPROM) */
115 /* #define CONFIG_SYS_I2C_EEPROM_ADDR   0x50 */ /* I2C boot EEPROM              */
116 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2       /* Bytes of address             */
117 /* #endif */
118
119 /*-----------------------------------------------------------------------
120  * Environment
121  *----------------------------------------------------------------------*/
122 /* #define CONFIG_SYS_NVRAM_SIZE        (0x2000 - 8) */ /* NVRAM size(8k)- RTC regs */
123
124 #undef  CONFIG_ENV_IS_IN_NVRAM          /* ... not in NVRAM             */
125 #define CONFIG_ENV_IS_IN_FLASH  1       /* Environment uses flash       */
126 #undef  CONFIG_ENV_IS_IN_EEPROM         /* ... not in EEPROM            */
127 #define CONFIG_ENV_OVERWRITE    1
128
129 /*
130  * Default environment variables
131  */
132 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
133         CONFIG_AMCC_DEF_ENV                                             \
134         CONFIG_AMCC_DEF_ENV_PPC                                         \
135         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
136         "kernel_addr=E7F10000\0"                                        \
137         "ramdisk_addr=E7F20000\0"                                       \
138         "pciconfighost=1\0"                                             \
139         "pcie_mode=RP:EP:EP\0"                                          \
140         ""
141
142 /*
143  * Commands additional to the ones defined in amcc-common.h
144  */
145 #define CONFIG_CMD_PCI
146 #define CONFIG_CMD_SDRAM
147
148 #define CONFIG_IBM_EMAC4_V4     1
149 #define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
150 #define CONFIG_HAS_ETH0
151 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
152 #define CONFIG_PHY_RESET_DELAY  1000
153 #define CONFIG_CIS8201_PHY      1       /* Enable 'special' RGMII mode for Cicada phy */
154 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
155
156 /*-----------------------------------------------------------------------
157  * FLASH related
158  *----------------------------------------------------------------------*/
159 #define CONFIG_SYS_MAX_FLASH_BANKS      3       /* number of banks              */
160 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* sectors per device           */
161
162 #undef  CONFIG_SYS_FLASH_CHECKSUM
163 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms) */
164 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms) */
165
166 #define CONFIG_SYS_FLASH_ADDR0          0x5555
167 #define CONFIG_SYS_FLASH_ADDR1          0x2aaa
168 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned char
169
170 #define CONFIG_SYS_FLASH_2ND_16BIT_DEV  1       /* evb440SPe has 8 and 16bit device */
171 #define CONFIG_SYS_FLASH_2ND_ADDR       0xe7c00000 /* evb440SPe has 8 and 16bit device*/
172
173 #ifdef CONFIG_ENV_IS_IN_FLASH
174 #define CONFIG_ENV_SECT_SIZE    0x10000 /* size of one complete sector  */
175 #define CONFIG_ENV_ADDR         0xfffa0000
176 /* #define CONFIG_ENV_ADDR              (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) */
177 #define CONFIG_ENV_SIZE         0x10000 /* Size of Environment vars     */
178 #endif /* CONFIG_ENV_IS_IN_FLASH */
179 /*-----------------------------------------------------------------------
180  * PCI stuff
181  *-----------------------------------------------------------------------
182  */
183 /* General PCI */
184 #define CONFIG_PCI                      /* include pci support          */
185 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
186 #define CONFIG_PCI_PNP          1       /* do pci plug-and-play         */
187 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
188 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
189
190 /* Board-specific PCI */
191 #define CONFIG_SYS_PCI_TARGET_INIT              /* let board init pci target    */
192 #undef  CONFIG_SYS_PCI_MASTER_INIT
193
194 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014   /* IBM                          */
195 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever                     */
196 /* #define CONFIG_SYS_PCI_SUBSYS_ID     CONFIG_SYS_PCI_SUBSYS_DEVICEID */
197
198 /*
199  *  NETWORK Support (PCI):
200  */
201 /* Support for Intel 82557/82559/82559ER chips. */
202 #define CONFIG_EEPRO100
203
204 /* FB Divisor selection */
205 #define FPGA_FB_DIV_6           6
206 #define FPGA_FB_DIV_10          10
207 #define FPGA_FB_DIV_12          12
208 #define FPGA_FB_DIV_20          20
209
210 /* VCO Divisor selection */
211 #define FPGA_VCO_DIV_4          4
212 #define FPGA_VCO_DIV_6          6
213 #define FPGA_VCO_DIV_8          8
214 #define FPGA_VCO_DIV_10         10
215
216 /*----------------------------------------------------------------------------+
217 | FPGA registers and bit definitions
218 +----------------------------------------------------------------------------*/
219 /* PowerPC 440SPe Board FPGA is reached with physical address 0x1 E2000000. */
220 /* TLB initialization makes it correspond to logical address 0xE2000000. */
221 /* => Done init_chip.s in bootlib */
222 #define FPGA_REG_BASE_ADDR      0xE2000000
223 #define FPGA_GPIO_BASE_ADDR     0xE2010000
224 #define FPGA_INT_BASE_ADDR      0xE2020000
225
226 /*----------------------------------------------------------------------------+
227 | Display
228 +----------------------------------------------------------------------------*/
229 #define PPC440SPE_DISPLAY       FPGA_REG_BASE_ADDR
230
231 #define PPC440SPE_DISPLAY_D8    (FPGA_REG_BASE_ADDR+0x06)
232 #define PPC440SPE_DISPLAY_D4    (FPGA_REG_BASE_ADDR+0x04)
233 #define PPC440SPE_DISPLAY_D2    (FPGA_REG_BASE_ADDR+0x02)
234 #define PPC440SPE_DISPLAY_D1    (FPGA_REG_BASE_ADDR+0x00)
235 /*define   WRITE_DISPLAY_DIGIT(n) IOREG8(FPGA_REG_BASE_ADDR + (2*n))*/
236 /*#define   IOREG8(addr) *((volatile unsigned char *)(addr))*/
237
238 /*----------------------------------------------------------------------------+
239 | ethernet/reset/boot Register 1
240 +----------------------------------------------------------------------------*/
241 #define FPGA_REG10      (FPGA_REG_BASE_ADDR+0x10)
242
243 #define FPGA_REG10_10MHZ_ENABLE         0x8000
244 #define FPGA_REG10_100MHZ_ENABLE        0x4000
245 #define FPGA_REG10_GIGABIT_ENABLE       0x2000
246 #define FPGA_REG10_FULL_DUPLEX          0x1000  /* force Full Duplex*/
247 #define FPGA_REG10_RESET_ETH            0x0800
248 #define FPGA_REG10_AUTO_NEG_DIS         0x0400
249 #define FPGA_REG10_INTP_ETH             0x0200
250
251 #define FPGA_REG10_RESET_HISR           0x0080
252 #define FPGA_REG10_ENABLE_DISPLAY       0x0040
253 #define FPGA_REG10_RESET_SDRAM          0x0020
254 #define FPGA_REG10_OPER_BOOT            0x0010
255 #define FPGA_REG10_SRAM_BOOT            0x0008
256 #define FPGA_REG10_SMALL_BOOT           0x0004
257 #define FPGA_REG10_FORCE_COLA           0x0002
258 #define FPGA_REG10_COLA_MANUAL          0x0001
259
260 #define FPGA_REG10_SDRAM_ENABLE         0x0020
261
262 #define FPGA_REG10_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*from ocotea ?*/
263 #define FPGA_REG10_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*from ocotea ?*/
264
265 /*----------------------------------------------------------------------------+
266 | MUX control
267 +----------------------------------------------------------------------------*/
268 #define FPGA_REG12      (FPGA_REG_BASE_ADDR+0x12)
269
270 #define FPGA_REG12_EBC_CTL              0x8000
271 #define FPGA_REG12_UART1_CTS_RTS        0x4000
272 #define FPGA_REG12_UART0_RX_ENABLE      0x2000
273 #define FPGA_REG12_UART1_RX_ENABLE      0x1000
274 #define FPGA_REG12_UART2_RX_ENABLE      0x0800
275 #define FPGA_REG12_EBC_OUT_ENABLE       0x0400
276 #define FPGA_REG12_GPIO0_OUT_ENABLE     0x0200
277 #define FPGA_REG12_GPIO1_OUT_ENABLE     0x0100
278 #define FPGA_REG12_GPIO_SELECT          0x0010
279 #define FPGA_REG12_GPIO_CHREG           0x0008
280 #define FPGA_REG12_GPIO_CLK_CHREG       0x0004
281 #define FPGA_REG12_GPIO_OETRI           0x0002
282 #define FPGA_REG12_EBC_ERROR            0x0001
283
284 /*----------------------------------------------------------------------------+
285 | PCI Clock control
286 +----------------------------------------------------------------------------*/
287 #define FPGA_REG16      (FPGA_REG_BASE_ADDR+0x16)
288
289 #define FPGA_REG16_PCI_CLK_CTL0         0x8000
290 #define FPGA_REG16_PCI_CLK_CTL1         0x4000
291 #define FPGA_REG16_PCI_CLK_CTL2         0x2000
292 #define FPGA_REG16_PCI_CLK_CTL3         0x1000
293 #define FPGA_REG16_PCI_CLK_CTL4         0x0800
294 #define FPGA_REG16_PCI_CLK_CTL5         0x0400
295 #define FPGA_REG16_PCI_CLK_CTL6         0x0200
296 #define FPGA_REG16_PCI_CLK_CTL7         0x0100
297 #define FPGA_REG16_PCI_CLK_CTL8         0x0080
298 #define FPGA_REG16_PCI_CLK_CTL9         0x0040
299 #define FPGA_REG16_PCI_EXT_ARB0         0x0020
300 #define FPGA_REG16_PCI_MODE_1           0x0010
301 #define FPGA_REG16_PCI_TARGET_MODE      0x0008
302 #define FPGA_REG16_PCI_INTP_MODE        0x0004
303
304 /* FB1 Divisor selection */
305 #define FPGA_REG16_FB2_DIV_MASK         0x1000
306 #define FPGA_REG16_FB2_DIV_LOW          0x0000
307 #define FPGA_REG16_FB2_DIV_HIGH         0x1000
308 /* FB2 Divisor selection */
309 /* S3 switch on Board */
310 #define FPGA_REG16_FB1_DIV_MASK         0x2000
311 #define FPGA_REG16_FB1_DIV_LOW          0x0000
312 #define FPGA_REG16_FB1_DIV_HIGH         0x2000
313 /* PCI0 Clock Selection */
314 /* S3 switch on Board */
315 #define FPGA_REG16_PCI0_CLK_MASK        0x0c00
316 #define FPGA_REG16_PCI0_CLK_33_33       0x0000
317 #define FPGA_REG16_PCI0_CLK_66_66       0x0800
318 #define FPGA_REG16_PCI0_CLK_100         0x0400
319 #define FPGA_REG16_PCI0_CLK_133_33      0x0c00
320 /* VCO Divisor selection */
321 /* S3 switch on Board */
322 #define FPGA_REG16_VCO_DIV_MASK         0xc000
323 #define FPGA_REG16_VCO_DIV_4            0x0000
324 #define FPGA_REG16_VCO_DIV_8            0x4000
325 #define FPGA_REG16_VCO_DIV_6            0x8000
326 #define FPGA_REG16_VCO_DIV_10           0xc000
327 /* Master Clock Selection */
328 /* S3, S4 switches on Board */
329 #define FPGA_REG16_MASTER_CLK_MASK      0x01c0
330 #define FPGA_REG16_MASTER_CLK_EXT       0x0000
331 #define FPGA_REG16_MASTER_CLK_66_66     0x0040
332 #define FPGA_REG16_MASTER_CLK_50        0x0080
333 #define FPGA_REG16_MASTER_CLK_33_33     0x00c0
334 #define FPGA_REG16_MASTER_CLK_25        0x0100
335
336 /*----------------------------------------------------------------------------+
337 | PCI Miscellaneous
338 +----------------------------------------------------------------------------*/
339 #define FPGA_REG18      (FPGA_REG_BASE_ADDR+0x18)
340
341 #define FPGA_REG18_PCI_PRSNT1           0x8000
342 #define FPGA_REG18_PCI_PRSNT2           0x4000
343 #define FPGA_REG18_PCI_INTA             0x2000
344 #define FPGA_REG18_PCI_SLOT0_INTP       0x1000
345 #define FPGA_REG18_PCI_SLOT1_INTP       0x0800
346 #define FPGA_REG18_PCI_SLOT2_INTP       0x0400
347 #define FPGA_REG18_PCI_SLOT3_INTP       0x0200
348 #define FPGA_REG18_PCI_PCI0_VC          0x0100
349 #define FPGA_REG18_PCI_PCI0_VTH1        0x0080
350 #define FPGA_REG18_PCI_PCI0_VTH2        0x0040
351 #define FPGA_REG18_PCI_PCI0_VTH3        0x0020
352
353 /*----------------------------------------------------------------------------+
354 | PCIe Miscellaneous
355 +----------------------------------------------------------------------------*/
356 #define FPGA_REG1A      (FPGA_REG_BASE_ADDR+0x1A)
357
358 #define FPGA_REG1A_PE0_GLED             0x8000
359 #define FPGA_REG1A_PE1_GLED             0x4000
360 #define FPGA_REG1A_PE2_GLED             0x2000
361 #define FPGA_REG1A_PE0_YLED             0x1000
362 #define FPGA_REG1A_PE1_YLED             0x0800
363 #define FPGA_REG1A_PE2_YLED             0x0400
364 #define FPGA_REG1A_PE0_PWRON            0x0200
365 #define FPGA_REG1A_PE1_PWRON            0x0100
366 #define FPGA_REG1A_PE2_PWRON            0x0080
367 #define FPGA_REG1A_PE0_REFCLK_ENABLE    0x0040
368 #define FPGA_REG1A_PE1_REFCLK_ENABLE    0x0020
369 #define FPGA_REG1A_PE2_REFCLK_ENABLE    0x0010
370 #define FPGA_REG1A_PE_SPREAD0           0x0008
371 #define FPGA_REG1A_PE_SPREAD1           0x0004
372 #define FPGA_REG1A_PE_SELSOURCE_0       0x0002
373 #define FPGA_REG1A_PE_SELSOURCE_1       0x0001
374
375 #define FPGA_REG1A_GLED_ENCODE(n)       (FPGA_REG1A_PE0_GLED >> (n))
376 #define FPGA_REG1A_YLED_ENCODE(n)       (FPGA_REG1A_PE0_YLED >> (n))
377 #define FPGA_REG1A_PWRON_ENCODE(n)      (FPGA_REG1A_PE0_PWRON >> (n))
378 #define FPGA_REG1A_REFCLK_ENCODE(n)     (FPGA_REG1A_PE0_REFCLK_ENABLE >> (n))
379
380 /*----------------------------------------------------------------------------+
381 | PCIe Miscellaneous
382 +----------------------------------------------------------------------------*/
383 #define FPGA_REG1C      (FPGA_REG_BASE_ADDR+0x1C)
384
385 #define FPGA_REG1C_PE0_ROOTPOINT        0x8000
386 #define FPGA_REG1C_PE1_ENDPOINT         0x4000
387 #define FPGA_REG1C_PE2_ENDPOINT         0x2000
388 #define FPGA_REG1C_PE0_PRSNT            0x1000
389 #define FPGA_REG1C_PE1_PRSNT            0x0800
390 #define FPGA_REG1C_PE2_PRSNT            0x0400
391 #define FPGA_REG1C_PE0_WAKE             0x0080
392 #define FPGA_REG1C_PE1_WAKE             0x0040
393 #define FPGA_REG1C_PE2_WAKE             0x0020
394 #define FPGA_REG1C_PE0_PERST            0x0010
395 #define FPGA_REG1C_PE1_PERST            0x0008
396 #define FPGA_REG1C_PE2_PERST            0x0004
397
398 #define FPGA_REG1C_ROOTPOINT_ENCODE(n)  (FPGA_REG1C_PE0_ROOTPOINT >> (n))
399 #define FPGA_REG1C_PERST_ENCODE(n)      (FPGA_REG1C_PE0_PERST >> (n))
400
401 /*----------------------------------------------------------------------------+
402 | Defines
403 +----------------------------------------------------------------------------*/
404 #define PERIOD_133_33MHZ        7500    /* 7,5ns */
405 #define PERIOD_100_00MHZ        10000   /* 10ns */
406 #define PERIOD_83_33MHZ         12000   /* 12ns */
407 #define PERIOD_75_00MHZ         13333   /* 13,333ns */
408 #define PERIOD_66_66MHZ         15000   /* 15ns */
409 #define PERIOD_50_00MHZ         20000   /* 20ns */
410 #define PERIOD_33_33MHZ         30000   /* 30ns */
411 #define PERIOD_25_00MHZ         40000   /* 40ns */
412
413 #endif  /* __CONFIG_H */