2 * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 /************************************************************************
24 * 1 january 2005 Alain Saurel <asaurel@amcc.com>
25 * Adapted to current Das U-Boot source
26 ***********************************************************************/
27 /************************************************************************
28 * yucca.h - configuration for AMCC 440SPe Ref (yucca)
29 ***********************************************************************/
34 /*-----------------------------------------------------------------------
35 * High Level Configuration Options
36 *----------------------------------------------------------------------*/
37 #define CONFIG_4xx 1 /* ... PPC4xx family */
38 #define CONFIG_440 1 /* ... PPC440 family */
39 #define CONFIG_440SPE 1 /* Specifc SPe support */
40 #define CONFIG_440SPE_REVA 1 /* Support old Rev A. */
41 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
42 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
43 #define EXTCLK_33_33 33333333
44 #define EXTCLK_66_66 66666666
45 #define EXTCLK_50 50000000
46 #define EXTCLK_83 83333333
49 * Include common defines/options for all AMCC eval boards
51 #define CONFIG_HOSTNAME yucca
52 #include "amcc-common.h"
54 #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
55 #undef CONFIG_SHOW_BOOT_PROGRESS
58 /*-----------------------------------------------------------------------
59 * Base addresses -- Note these are effective addresses where the
60 * actual resources get mapped (not physical addresses)
61 *----------------------------------------------------------------------*/
62 #define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */
63 #define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */
65 #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
66 #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
67 #define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
69 #define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
70 #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
71 #define CONFIG_SYS_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
73 #define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000
74 #define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000
75 #define CONFIG_SYS_PCIE2_CFGBASE 0xc2000000
76 #define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
77 #define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
78 #define CONFIG_SYS_PCIE2_XCFGBASE 0xc3002000
80 /* base address of inbound PCIe window */
81 #define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000400000000ULL
83 /* System RAM mapped to PCI space */
84 #define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
85 #define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
86 #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
88 #define CONFIG_SYS_FPGA_BASE 0xe2000000 /* epld */
89 #define CONFIG_SYS_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */
91 /* #define CONFIG_SYS_NVRAM_BASE_ADDR 0x08000000 */
92 /*-----------------------------------------------------------------------
93 * Initial RAM & stack pointer (placed in internal SRAM)
94 *----------------------------------------------------------------------*/
95 #define CONFIG_SYS_TEMP_STACK_OCM 1
96 #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
97 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
98 #define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
99 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
101 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
102 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
104 /*-----------------------------------------------------------------------
106 *----------------------------------------------------------------------*/
107 #define CONFIG_CONS_INDEX 1 /* Use UART0 */
109 #undef CONFIG_SYS_EXT_SERIAL_CLOCK
110 /* #define CONFIG_SYS_EXT_SERIAL_CLOCK (1843200 * 6) */ /* Ext clk @ 11.059 MHz */
112 /*-----------------------------------------------------------------------
114 *----------------------------------------------------------------------*/
115 #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
116 #define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/
117 #define CONFIG_DDR_ECC 1 /* with ECC support */
119 /*-----------------------------------------------------------------------
121 *----------------------------------------------------------------------*/
122 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
124 #define IIC0_BOOTPROM_ADDR 0x50
125 #define IIC0_ALT_BOOTPROM_ADDR 0x54
127 /* Don't probe these addrs */
128 #define CONFIG_SYS_I2C_NOPROBES {0x50, 0x52, 0x53, 0x54}
130 /* #if defined(CONFIG_CMD_EEPROM) */
131 /* #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 */ /* I2C boot EEPROM */
132 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
135 /*-----------------------------------------------------------------------
137 *----------------------------------------------------------------------*/
138 /* #define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) */ /* NVRAM size(8k)- RTC regs */
140 #undef CONFIG_ENV_IS_IN_NVRAM /* ... not in NVRAM */
141 #define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
142 #undef CONFIG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
143 #define CONFIG_ENV_OVERWRITE 1
146 * Default environment variables
148 #define CONFIG_EXTRA_ENV_SETTINGS \
149 CONFIG_AMCC_DEF_ENV \
150 CONFIG_AMCC_DEF_ENV_PPC \
151 CONFIG_AMCC_DEF_ENV_NOR_UPD \
152 "kernel_addr=E7F10000\0" \
153 "ramdisk_addr=E7F20000\0" \
154 "pciconfighost=1\0" \
155 "pcie_mode=RP:EP:EP\0" \
159 * Commands additional to the ones defined in amcc-common.h
161 #define CONFIG_CMD_PCI
162 #define CONFIG_CMD_SDRAM
164 #define CONFIG_IBM_EMAC4_V4 1
165 #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
166 #define CONFIG_HAS_ETH0
167 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
168 #define CONFIG_PHY_RESET_DELAY 1000
169 #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
170 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
172 /*-----------------------------------------------------------------------
174 *----------------------------------------------------------------------*/
175 #define CONFIG_SYS_MAX_FLASH_BANKS 3 /* number of banks */
176 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
178 #undef CONFIG_SYS_FLASH_CHECKSUM
179 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
180 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
182 #define CONFIG_SYS_FLASH_ADDR0 0x5555
183 #define CONFIG_SYS_FLASH_ADDR1 0x2aaa
184 #define CONFIG_SYS_FLASH_WORD_SIZE unsigned char
186 #define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* evb440SPe has 8 and 16bit device */
187 #define CONFIG_SYS_FLASH_2ND_ADDR 0xe7c00000 /* evb440SPe has 8 and 16bit device*/
189 #ifdef CONFIG_ENV_IS_IN_FLASH
190 #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
191 #define CONFIG_ENV_ADDR 0xfffa0000
192 /* #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) */
193 #define CONFIG_ENV_SIZE 0x10000 /* Size of Environment vars */
194 #endif /* CONFIG_ENV_IS_IN_FLASH */
195 /*-----------------------------------------------------------------------
197 *-----------------------------------------------------------------------
200 #define CONFIG_PCI /* include pci support */
201 #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
202 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
203 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
205 /* Board-specific PCI */
206 #define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
207 #undef CONFIG_SYS_PCI_MASTER_INIT
209 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
210 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
211 /* #define CONFIG_SYS_PCI_SUBSYS_ID CONFIG_SYS_PCI_SUBSYS_DEVICEID */
214 * NETWORK Support (PCI):
216 /* Support for Intel 82557/82559/82559ER chips. */
217 #define CONFIG_EEPRO100
219 /* FB Divisor selection */
220 #define FPGA_FB_DIV_6 6
221 #define FPGA_FB_DIV_10 10
222 #define FPGA_FB_DIV_12 12
223 #define FPGA_FB_DIV_20 20
225 /* VCO Divisor selection */
226 #define FPGA_VCO_DIV_4 4
227 #define FPGA_VCO_DIV_6 6
228 #define FPGA_VCO_DIV_8 8
229 #define FPGA_VCO_DIV_10 10
231 /*----------------------------------------------------------------------------+
232 | FPGA registers and bit definitions
233 +----------------------------------------------------------------------------*/
234 /* PowerPC 440SPe Board FPGA is reached with physical address 0x1 E2000000. */
235 /* TLB initialization makes it correspond to logical address 0xE2000000. */
236 /* => Done init_chip.s in bootlib */
237 #define FPGA_REG_BASE_ADDR 0xE2000000
238 #define FPGA_GPIO_BASE_ADDR 0xE2010000
239 #define FPGA_INT_BASE_ADDR 0xE2020000
241 /*----------------------------------------------------------------------------+
243 +----------------------------------------------------------------------------*/
244 #define PPC440SPE_DISPLAY FPGA_REG_BASE_ADDR
246 #define PPC440SPE_DISPLAY_D8 (FPGA_REG_BASE_ADDR+0x06)
247 #define PPC440SPE_DISPLAY_D4 (FPGA_REG_BASE_ADDR+0x04)
248 #define PPC440SPE_DISPLAY_D2 (FPGA_REG_BASE_ADDR+0x02)
249 #define PPC440SPE_DISPLAY_D1 (FPGA_REG_BASE_ADDR+0x00)
250 /*define WRITE_DISPLAY_DIGIT(n) IOREG8(FPGA_REG_BASE_ADDR + (2*n))*/
251 /*#define IOREG8(addr) *((volatile unsigned char *)(addr))*/
253 /*----------------------------------------------------------------------------+
254 | ethernet/reset/boot Register 1
255 +----------------------------------------------------------------------------*/
256 #define FPGA_REG10 (FPGA_REG_BASE_ADDR+0x10)
258 #define FPGA_REG10_10MHZ_ENABLE 0x8000
259 #define FPGA_REG10_100MHZ_ENABLE 0x4000
260 #define FPGA_REG10_GIGABIT_ENABLE 0x2000
261 #define FPGA_REG10_FULL_DUPLEX 0x1000 /* force Full Duplex*/
262 #define FPGA_REG10_RESET_ETH 0x0800
263 #define FPGA_REG10_AUTO_NEG_DIS 0x0400
264 #define FPGA_REG10_INTP_ETH 0x0200
266 #define FPGA_REG10_RESET_HISR 0x0080
267 #define FPGA_REG10_ENABLE_DISPLAY 0x0040
268 #define FPGA_REG10_RESET_SDRAM 0x0020
269 #define FPGA_REG10_OPER_BOOT 0x0010
270 #define FPGA_REG10_SRAM_BOOT 0x0008
271 #define FPGA_REG10_SMALL_BOOT 0x0004
272 #define FPGA_REG10_FORCE_COLA 0x0002
273 #define FPGA_REG10_COLA_MANUAL 0x0001
275 #define FPGA_REG10_SDRAM_ENABLE 0x0020
277 #define FPGA_REG10_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*from ocotea ?*/
278 #define FPGA_REG10_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*from ocotea ?*/
280 /*----------------------------------------------------------------------------+
282 +----------------------------------------------------------------------------*/
283 #define FPGA_REG12 (FPGA_REG_BASE_ADDR+0x12)
285 #define FPGA_REG12_EBC_CTL 0x8000
286 #define FPGA_REG12_UART1_CTS_RTS 0x4000
287 #define FPGA_REG12_UART0_RX_ENABLE 0x2000
288 #define FPGA_REG12_UART1_RX_ENABLE 0x1000
289 #define FPGA_REG12_UART2_RX_ENABLE 0x0800
290 #define FPGA_REG12_EBC_OUT_ENABLE 0x0400
291 #define FPGA_REG12_GPIO0_OUT_ENABLE 0x0200
292 #define FPGA_REG12_GPIO1_OUT_ENABLE 0x0100
293 #define FPGA_REG12_GPIO_SELECT 0x0010
294 #define FPGA_REG12_GPIO_CHREG 0x0008
295 #define FPGA_REG12_GPIO_CLK_CHREG 0x0004
296 #define FPGA_REG12_GPIO_OETRI 0x0002
297 #define FPGA_REG12_EBC_ERROR 0x0001
299 /*----------------------------------------------------------------------------+
301 +----------------------------------------------------------------------------*/
302 #define FPGA_REG16 (FPGA_REG_BASE_ADDR+0x16)
304 #define FPGA_REG16_PCI_CLK_CTL0 0x8000
305 #define FPGA_REG16_PCI_CLK_CTL1 0x4000
306 #define FPGA_REG16_PCI_CLK_CTL2 0x2000
307 #define FPGA_REG16_PCI_CLK_CTL3 0x1000
308 #define FPGA_REG16_PCI_CLK_CTL4 0x0800
309 #define FPGA_REG16_PCI_CLK_CTL5 0x0400
310 #define FPGA_REG16_PCI_CLK_CTL6 0x0200
311 #define FPGA_REG16_PCI_CLK_CTL7 0x0100
312 #define FPGA_REG16_PCI_CLK_CTL8 0x0080
313 #define FPGA_REG16_PCI_CLK_CTL9 0x0040
314 #define FPGA_REG16_PCI_EXT_ARB0 0x0020
315 #define FPGA_REG16_PCI_MODE_1 0x0010
316 #define FPGA_REG16_PCI_TARGET_MODE 0x0008
317 #define FPGA_REG16_PCI_INTP_MODE 0x0004
319 /* FB1 Divisor selection */
320 #define FPGA_REG16_FB2_DIV_MASK 0x1000
321 #define FPGA_REG16_FB2_DIV_LOW 0x0000
322 #define FPGA_REG16_FB2_DIV_HIGH 0x1000
323 /* FB2 Divisor selection */
324 /* S3 switch on Board */
325 #define FPGA_REG16_FB1_DIV_MASK 0x2000
326 #define FPGA_REG16_FB1_DIV_LOW 0x0000
327 #define FPGA_REG16_FB1_DIV_HIGH 0x2000
328 /* PCI0 Clock Selection */
329 /* S3 switch on Board */
330 #define FPGA_REG16_PCI0_CLK_MASK 0x0c00
331 #define FPGA_REG16_PCI0_CLK_33_33 0x0000
332 #define FPGA_REG16_PCI0_CLK_66_66 0x0800
333 #define FPGA_REG16_PCI0_CLK_100 0x0400
334 #define FPGA_REG16_PCI0_CLK_133_33 0x0c00
335 /* VCO Divisor selection */
336 /* S3 switch on Board */
337 #define FPGA_REG16_VCO_DIV_MASK 0xc000
338 #define FPGA_REG16_VCO_DIV_4 0x0000
339 #define FPGA_REG16_VCO_DIV_8 0x4000
340 #define FPGA_REG16_VCO_DIV_6 0x8000
341 #define FPGA_REG16_VCO_DIV_10 0xc000
342 /* Master Clock Selection */
343 /* S3, S4 switches on Board */
344 #define FPGA_REG16_MASTER_CLK_MASK 0x01c0
345 #define FPGA_REG16_MASTER_CLK_EXT 0x0000
346 #define FPGA_REG16_MASTER_CLK_66_66 0x0040
347 #define FPGA_REG16_MASTER_CLK_50 0x0080
348 #define FPGA_REG16_MASTER_CLK_33_33 0x00c0
349 #define FPGA_REG16_MASTER_CLK_25 0x0100
351 /*----------------------------------------------------------------------------+
353 +----------------------------------------------------------------------------*/
354 #define FPGA_REG18 (FPGA_REG_BASE_ADDR+0x18)
356 #define FPGA_REG18_PCI_PRSNT1 0x8000
357 #define FPGA_REG18_PCI_PRSNT2 0x4000
358 #define FPGA_REG18_PCI_INTA 0x2000
359 #define FPGA_REG18_PCI_SLOT0_INTP 0x1000
360 #define FPGA_REG18_PCI_SLOT1_INTP 0x0800
361 #define FPGA_REG18_PCI_SLOT2_INTP 0x0400
362 #define FPGA_REG18_PCI_SLOT3_INTP 0x0200
363 #define FPGA_REG18_PCI_PCI0_VC 0x0100
364 #define FPGA_REG18_PCI_PCI0_VTH1 0x0080
365 #define FPGA_REG18_PCI_PCI0_VTH2 0x0040
366 #define FPGA_REG18_PCI_PCI0_VTH3 0x0020
368 /*----------------------------------------------------------------------------+
370 +----------------------------------------------------------------------------*/
371 #define FPGA_REG1A (FPGA_REG_BASE_ADDR+0x1A)
373 #define FPGA_REG1A_PE0_GLED 0x8000
374 #define FPGA_REG1A_PE1_GLED 0x4000
375 #define FPGA_REG1A_PE2_GLED 0x2000
376 #define FPGA_REG1A_PE0_YLED 0x1000
377 #define FPGA_REG1A_PE1_YLED 0x0800
378 #define FPGA_REG1A_PE2_YLED 0x0400
379 #define FPGA_REG1A_PE0_PWRON 0x0200
380 #define FPGA_REG1A_PE1_PWRON 0x0100
381 #define FPGA_REG1A_PE2_PWRON 0x0080
382 #define FPGA_REG1A_PE0_REFCLK_ENABLE 0x0040
383 #define FPGA_REG1A_PE1_REFCLK_ENABLE 0x0020
384 #define FPGA_REG1A_PE2_REFCLK_ENABLE 0x0010
385 #define FPGA_REG1A_PE_SPREAD0 0x0008
386 #define FPGA_REG1A_PE_SPREAD1 0x0004
387 #define FPGA_REG1A_PE_SELSOURCE_0 0x0002
388 #define FPGA_REG1A_PE_SELSOURCE_1 0x0001
390 #define FPGA_REG1A_GLED_ENCODE(n) (FPGA_REG1A_PE0_GLED >> (n))
391 #define FPGA_REG1A_YLED_ENCODE(n) (FPGA_REG1A_PE0_YLED >> (n))
392 #define FPGA_REG1A_PWRON_ENCODE(n) (FPGA_REG1A_PE0_PWRON >> (n))
393 #define FPGA_REG1A_REFCLK_ENCODE(n) (FPGA_REG1A_PE0_REFCLK_ENABLE >> (n))
395 /*----------------------------------------------------------------------------+
397 +----------------------------------------------------------------------------*/
398 #define FPGA_REG1C (FPGA_REG_BASE_ADDR+0x1C)
400 #define FPGA_REG1C_PE0_ROOTPOINT 0x8000
401 #define FPGA_REG1C_PE1_ENDPOINT 0x4000
402 #define FPGA_REG1C_PE2_ENDPOINT 0x2000
403 #define FPGA_REG1C_PE0_PRSNT 0x1000
404 #define FPGA_REG1C_PE1_PRSNT 0x0800
405 #define FPGA_REG1C_PE2_PRSNT 0x0400
406 #define FPGA_REG1C_PE0_WAKE 0x0080
407 #define FPGA_REG1C_PE1_WAKE 0x0040
408 #define FPGA_REG1C_PE2_WAKE 0x0020
409 #define FPGA_REG1C_PE0_PERST 0x0010
410 #define FPGA_REG1C_PE1_PERST 0x0008
411 #define FPGA_REG1C_PE2_PERST 0x0004
413 #define FPGA_REG1C_ROOTPOINT_ENCODE(n) (FPGA_REG1C_PE0_ROOTPOINT >> (n))
414 #define FPGA_REG1C_PERST_ENCODE(n) (FPGA_REG1C_PE0_PERST >> (n))
416 /*----------------------------------------------------------------------------+
418 +----------------------------------------------------------------------------*/
419 #define PERIOD_133_33MHZ 7500 /* 7,5ns */
420 #define PERIOD_100_00MHZ 10000 /* 10ns */
421 #define PERIOD_83_33MHZ 12000 /* 12ns */
422 #define PERIOD_75_00MHZ 13333 /* 13,333ns */
423 #define PERIOD_66_66MHZ 15000 /* 15ns */
424 #define PERIOD_50_00MHZ 20000 /* 20ns */
425 #define PERIOD_33_33MHZ 30000 /* 30ns */
426 #define PERIOD_25_00MHZ 40000 /* 40ns */
428 #endif /* __CONFIG_H */