2 * Copyright 2008 Extreme Engineering Solutions, Inc.
3 * Copyright 2004-2008 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
9 * xpedite520x board configuration file
15 * High Level Configuration Options
17 #define CONFIG_SYS_BOARD_NAME "XPedite5200"
18 #define CONFIG_SYS_FORM_PMC_XMC 1
19 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
21 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
22 #define CONFIG_PCI1 1 /* PCI controller 1 */
23 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
24 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
25 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
30 #undef CONFIG_FSL_DDR_INTERACTIVE
31 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
32 #define CONFIG_DDR_SPD
33 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
34 #define SPD_EEPROM_ADDRESS 0x54
35 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
36 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
37 #define CONFIG_DDR_ECC
38 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
39 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
40 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
41 #define CONFIG_VERY_BIG_RAM
43 #define CONFIG_SYS_CLK_FREQ 66666666
46 * These can be toggled for performance analysis, otherwise use default.
48 #define CONFIG_L2_CACHE /* toggle L2 cache */
49 #define CONFIG_BTB /* toggle branch predition */
50 #define CONFIG_ENABLE_36BIT_PHYS 1
52 #define CONFIG_SYS_CCSRBAR 0xef000000
53 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
58 #define CONFIG_SYS_MEMTEST_START 0x10000000
59 #define CONFIG_SYS_MEMTEST_END 0x20000000
60 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
62 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \
63 CONFIG_SYS_I2C_EEPROM_ADDR, \
64 CONFIG_SYS_I2C_PCA953X_ADDR0, \
65 CONFIG_SYS_I2C_PCA953X_ADDR1, \
66 CONFIG_SYS_I2C_RTC_ADDR}
70 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
71 * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable
72 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
73 * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable
74 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
75 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
76 * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable
77 * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable
80 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
83 * NAND flash configuration
85 #define CONFIG_SYS_NAND_BASE 0xef800000
86 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
87 #define CONFIG_SYS_MAX_NAND_DEVICE 1
88 #define CONFIG_NAND_ACTL
89 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */
90 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */
91 #define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */
92 #define CONFIG_SYS_NAND_ACTL_DELAY 25
95 * NOR flash configuration
97 #define CONFIG_SYS_FLASH_BASE 0xfc000000
98 #define CONFIG_SYS_FLASH_BASE2 0xf8000000
99 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
100 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
101 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
102 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
103 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
104 #define CONFIG_FLASH_CFI_DRIVER
105 #define CONFIG_SYS_FLASH_CFI
106 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
107 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
108 {0xfbf40000, 0xc0000} }
109 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
112 * Chip select configuration
114 /* NOR Flash 0 on CS0 */
115 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
118 #define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \
122 /* NOR Flash 1 on CS1 */
123 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
126 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
128 /* NAND flash on CS2 */
129 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
133 /* NAND flash on CS2 */
134 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
142 /* NAND flash on CS3 */
143 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
146 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
149 * Use L1 as initial stack
151 #define CONFIG_SYS_INIT_RAM_LOCK 1
152 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
153 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000
155 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
156 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
158 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
159 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
164 #define CONFIG_SYS_NS16550_SERIAL
165 #define CONFIG_SYS_NS16550_REG_SIZE 1
166 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
167 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
168 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
169 #define CONFIG_SYS_BAUDRATE_TABLE \
170 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
171 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
172 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
177 #define CONFIG_SYS_I2C
178 #define CONFIG_SYS_I2C_FSL
179 #define CONFIG_SYS_FSL_I2C_SPEED 400000
180 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
181 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
182 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
183 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
184 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
187 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
188 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
189 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
190 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
193 #define CONFIG_RTC_M41T11 1
194 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
195 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
198 #define CONFIG_PCA953X
199 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
200 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19
201 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
204 #define CONFIG_SYS_PCA953X_BRD_CFG0 0x01
205 #define CONFIG_SYS_PCA953X_BRD_CFG1 0x02
206 #define CONFIG_SYS_PCA953X_BRD_CFG2 0x04
207 #define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08
208 #define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10
209 #define CONFIG_SYS_PCA953X_NVM_WP 0x20
210 #define CONFIG_SYS_PCA953X_MONARCH 0x40
211 #define CONFIG_SYS_PCA953X_EREADY 0x80
214 #define CONFIG_SYS_PCA953X_P14_IO0 0x01
215 #define CONFIG_SYS_PCA953X_P14_IO1 0x02
216 #define CONFIG_SYS_PCA953X_P14_IO2 0x04
217 #define CONFIG_SYS_PCA953X_P14_IO3 0x08
218 #define CONFIG_SYS_PCA953X_P14_IO4 0x10
219 #define CONFIG_SYS_PCA953X_P14_IO5 0x20
220 #define CONFIG_SYS_PCA953X_P14_IO6 0x40
221 #define CONFIG_SYS_PCA953X_P14_IO7 0x80
223 /* 12-bit ADC used to measure CPU diode */
224 #define CONFIG_SYS_I2C_MAX1237_ADDR 0x34
228 * Memory space is mapped 1-1, but I/O space must start from 0.
230 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
231 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
232 #define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */
233 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
234 #define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000
235 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */
240 #define CONFIG_TSEC_ENET /* tsec ethernet support */
241 #define CONFIG_MII 1 /* MII PHY management */
242 #define CONFIG_ETHPRIME "eTSEC1"
244 #define CONFIG_TSEC1 1
245 #define CONFIG_TSEC1_NAME "eTSEC1"
246 #define TSEC1_FLAGS TSEC_GIGABIT
247 #define TSEC1_PHY_ADDR 1
248 #define TSEC1_PHYIDX 0
249 #define CONFIG_HAS_ETH0
251 #define CONFIG_TSEC2 1
252 #define CONFIG_TSEC2_NAME "eTSEC2"
253 #define TSEC2_FLAGS TSEC_GIGABIT
254 #define TSEC2_PHY_ADDR 2
255 #define TSEC2_PHYIDX 0
256 #define CONFIG_HAS_ETH1
258 #define CONFIG_TSEC3 1
259 #define CONFIG_TSEC3_NAME "eTSEC3"
260 #define TSEC3_FLAGS TSEC_GIGABIT
261 #define TSEC3_PHY_ADDR 3
262 #define TSEC3_PHYIDX 0
263 #define CONFIG_HAS_ETH2
265 #define CONFIG_TSEC4 1
266 #define CONFIG_TSEC4_NAME "eTSEC4"
267 #define TSEC4_FLAGS TSEC_GIGABIT
268 #define TSEC4_PHY_ADDR 4
269 #define TSEC4_PHYIDX 0
270 #define CONFIG_HAS_ETH3
275 #define CONFIG_BOOTP_BOOTFILESIZE
278 * Miscellaneous configurable options
280 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
281 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
282 #define CONFIG_PREBOOT /* enable preboot variable */
283 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
284 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
287 * For booting Linux, the board info and command line data
288 * have to be in the first 16 MB of memory, since this is
289 * the maximum mapped by the Linux kernel during initialization.
291 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
292 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
295 * Environment Configuration
297 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
298 #define CONFIG_ENV_SIZE 0x8000
299 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
303 * fff80000 - ffffffff Pri U-Boot (512 KB)
304 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
305 * fff00000 - fff3ffff Pri FDT (256KB)
306 * fef00000 - ffefffff Pri OS image (16MB)
307 * fc000000 - feefffff Pri OS Use/Filesystem (47MB)
309 * fbf80000 - fbffffff Sec U-Boot (512 KB)
310 * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB)
311 * fbf00000 - fbf3ffff Sec FDT (256KB)
312 * faf00000 - fbefffff Sec OS image (16MB)
313 * f8000000 - faefffff Sec OS Use/Filesystem (47MB)
315 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
316 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xfbf80000)
317 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
318 #define CONFIG_FDT2_ENV_ADDR __stringify(0xfbf00000)
319 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
320 #define CONFIG_OS2_ENV_ADDR __stringify(0xfaf00000)
322 #define CONFIG_PROG_UBOOT1 \
323 "$download_cmd $loadaddr $ubootfile; " \
324 "if test $? -eq 0; then " \
325 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
326 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
327 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
328 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
329 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
330 "if test $? -ne 0; then " \
331 "echo PROGRAM FAILED; " \
333 "echo PROGRAM SUCCEEDED; " \
336 "echo DOWNLOAD FAILED; " \
339 #define CONFIG_PROG_UBOOT2 \
340 "$download_cmd $loadaddr $ubootfile; " \
341 "if test $? -eq 0; then " \
342 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
343 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
344 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
345 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
346 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
347 "if test $? -ne 0; then " \
348 "echo PROGRAM FAILED; " \
350 "echo PROGRAM SUCCEEDED; " \
353 "echo DOWNLOAD FAILED; " \
356 #define CONFIG_BOOT_OS_NET \
357 "$download_cmd $osaddr $osfile; " \
358 "if test $? -eq 0; then " \
359 "if test -n $fdtaddr; then " \
360 "$download_cmd $fdtaddr $fdtfile; " \
361 "if test $? -eq 0; then " \
362 "bootm $osaddr - $fdtaddr; " \
364 "echo FDT DOWNLOAD FAILED; " \
370 "echo OS DOWNLOAD FAILED; " \
373 #define CONFIG_PROG_OS1 \
374 "$download_cmd $osaddr $osfile; " \
375 "if test $? -eq 0; then " \
376 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
377 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
378 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
379 "if test $? -ne 0; then " \
380 "echo OS PROGRAM FAILED; " \
382 "echo OS PROGRAM SUCCEEDED; " \
385 "echo OS DOWNLOAD FAILED; " \
388 #define CONFIG_PROG_OS2 \
389 "$download_cmd $osaddr $osfile; " \
390 "if test $? -eq 0; then " \
391 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
392 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
393 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
394 "if test $? -ne 0; then " \
395 "echo OS PROGRAM FAILED; " \
397 "echo OS PROGRAM SUCCEEDED; " \
400 "echo OS DOWNLOAD FAILED; " \
403 #define CONFIG_PROG_FDT1 \
404 "$download_cmd $fdtaddr $fdtfile; " \
405 "if test $? -eq 0; then " \
406 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
407 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
408 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
409 "if test $? -ne 0; then " \
410 "echo FDT PROGRAM FAILED; " \
412 "echo FDT PROGRAM SUCCEEDED; " \
415 "echo FDT DOWNLOAD FAILED; " \
418 #define CONFIG_PROG_FDT2 \
419 "$download_cmd $fdtaddr $fdtfile; " \
420 "if test $? -eq 0; then " \
421 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
422 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
423 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
424 "if test $? -ne 0; then " \
425 "echo FDT PROGRAM FAILED; " \
427 "echo FDT PROGRAM SUCCEEDED; " \
430 "echo FDT DOWNLOAD FAILED; " \
433 #define CONFIG_EXTRA_ENV_SETTINGS \
435 "download_cmd=tftp\0" \
436 "console_args=console=ttyS0,115200\0" \
437 "root_args=root=/dev/nfs rw\0" \
438 "misc_args=ip=on\0" \
439 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
440 "bootfile=/home/user/file\0" \
441 "osfile=/home/user/board.uImage\0" \
442 "fdtfile=/home/user/board.dtb\0" \
443 "ubootfile=/home/user/u-boot.bin\0" \
444 "fdtaddr=0x1e00000\0" \
445 "osaddr=0x1000000\0" \
446 "loadaddr=0x1000000\0" \
447 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
448 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
449 "prog_os1="CONFIG_PROG_OS1"\0" \
450 "prog_os2="CONFIG_PROG_OS2"\0" \
451 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
452 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
453 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
454 "bootcmd_flash1=run set_bootargs; " \
455 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
456 "bootcmd_flash2=run set_bootargs; " \
457 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
458 "bootcmd=run bootcmd_flash1\0"
459 #endif /* __CONFIG_H */