2 * Copyright 2009 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
9 * xpedite517x board configuration file
15 * High Level Configuration Options
17 #define CONFIG_SYS_BOARD_NAME "XPedite5170"
18 #define CONFIG_SYS_FORM_3U_VPX 1
19 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
20 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
21 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */
22 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
23 #define CONFIG_ALTIVEC 1
25 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
26 #define CONFIG_PCIE1 1 /* PCIE controller 1 */
27 #define CONFIG_PCIE2 1 /* PCIE controller 2 */
28 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
29 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
30 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
35 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
36 #define CONFIG_DDR_SPD
37 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
38 #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
39 #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
40 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
41 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
42 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
43 #define CONFIG_DDR_ECC
44 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
45 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
46 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
47 #define CONFIG_VERY_BIG_RAM
48 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
51 * virtual address to be used for temporary mappings. There
52 * should be 128k free at this VA.
54 #define CONFIG_SYS_SCRATCH_VA 0xe0000000
57 extern unsigned long get_board_sys_clk(unsigned long dummy);
60 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */
67 #define L2_ENABLE (L2CR_L2E)
70 * Base addresses -- Note these are effective addresses where the
71 * actual resources get mapped (not physical addresses)
73 #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
74 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
75 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
76 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
77 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
82 #define CONFIG_SYS_ALT_MEMTEST
83 #define CONFIG_SYS_MEMTEST_START 0x10000000
84 #define CONFIG_SYS_MEMTEST_END 0x20000000
85 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\
87 /* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
88 #define I2C_ADDR_IGNORE_LIST {0x50}
92 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
93 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
94 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
95 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
96 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
97 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
98 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
99 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
100 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
101 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
104 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
107 * NAND flash configuration
109 #define CONFIG_SYS_NAND_BASE 0xef800000
110 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
111 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
112 #define CONFIG_SYS_MAX_NAND_DEVICE 2
113 #define CONFIG_NAND_ACTL
114 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */
115 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */
116 #define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */
117 #define CONFIG_SYS_NAND_ACTL_DELAY 25
118 #define CONFIG_JFFS2_NAND
121 * NOR flash configuration
123 #define CONFIG_SYS_FLASH_BASE 0xf8000000
124 #define CONFIG_SYS_FLASH_BASE2 0xf0000000
125 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
126 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
127 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
128 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
129 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
130 #define CONFIG_FLASH_CFI_DRIVER
131 #define CONFIG_SYS_FLASH_CFI
132 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
133 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \
134 {0xf7f00000, 0xc0000} }
135 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
136 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
139 * Chip select configuration
141 /* NOR Flash 0 on CS0 */
142 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
145 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\
154 /* NOR Flash 1 on CS1 */
155 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\
158 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
160 /* NAND flash on CS2 */
161 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\
164 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\
172 /* Optional NAND flash on CS3 */
173 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\
176 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
179 * Use L1 as initial stack
181 #define CONFIG_SYS_INIT_RAM_LOCK 1
182 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
183 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
185 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
186 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
188 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
189 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
194 #define CONFIG_SYS_NS16550_SERIAL
195 #define CONFIG_SYS_NS16550_REG_SIZE 1
196 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
197 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
198 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
199 #define CONFIG_SYS_BAUDRATE_TABLE \
200 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
201 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
202 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
207 #define CONFIG_SYS_I2C
208 #define CONFIG_SYS_I2C_FSL
209 #define CONFIG_SYS_FSL_I2C_SPEED 100000
210 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
211 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
212 #define CONFIG_SYS_FSL_I2C2_SPEED 100000
213 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
214 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
216 /* PEX8518 slave I2C interface */
217 #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
219 /* I2C DS1631 temperature sensor */
220 #define CONFIG_SYS_I2C_LM90_ADDR 0x4c
222 /* I2C EEPROM - AT24C128B */
223 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
224 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
225 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
226 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
229 #define CONFIG_RTC_M41T11 1
230 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
231 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
234 #define CONFIG_PCA953X
235 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
236 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
237 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
238 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
239 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
240 #define CONFIG_SYS_I2C_PCA9553_ADDR 0x62
243 * PU = pulled high, PD = pulled low
244 * I = input, O = output, IO = input/output
247 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
248 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
249 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
250 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
251 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
252 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
255 #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
256 #define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */
257 #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
258 #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
259 #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
260 #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
261 #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
262 #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
265 #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
266 #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
267 #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
268 #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
269 #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
270 #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */
271 #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */
274 #define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */
275 #define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */
276 #define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */
277 #define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */
281 * Memory space is mapped 1-1, but I/O space must start from 0.
283 /* PCIE1 - PEX8518 */
284 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
285 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
286 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
287 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
288 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
289 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
292 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
293 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
294 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
295 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
296 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
297 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
302 #define CONFIG_TSEC_ENET /* tsec ethernet support */
303 #define CONFIG_MII 1 /* MII PHY management */
304 #define CONFIG_ETHPRIME "eTSEC1"
306 #define CONFIG_TSEC1 1
307 #define CONFIG_TSEC1_NAME "eTSEC1"
308 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
309 #define TSEC1_PHY_ADDR 1
310 #define TSEC1_PHYIDX 0
311 #define CONFIG_HAS_ETH0
313 #define CONFIG_TSEC2 1
314 #define CONFIG_TSEC2_NAME "eTSEC2"
315 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
316 #define TSEC2_PHY_ADDR 2
317 #define TSEC2_PHYIDX 0
318 #define CONFIG_HAS_ETH1
323 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
324 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
328 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\
332 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
335 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
339 * BAT0 2G Cacheable, non-guarded
342 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
343 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
344 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
345 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
348 * BAT1 1G Cache-inhibited, guarded
349 * 0x8000_0000 1G PCI-Express 1 Memory
351 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
355 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\
359 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
362 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
365 * BAT2 512M Cache-inhibited, guarded
366 * 0xc000_0000 512M PCI-Express 2 Memory
368 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
372 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\
376 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
379 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
382 * BAT3 1M Cache-inhibited, guarded
383 * 0xe000_0000 1M CCSR
385 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\
389 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\
393 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\
396 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
399 * BAT4 32M Cache-inhibited, guarded
400 * 0xe200_0000 16M PCI-Express 1 I/O
401 * 0xe300_0000 16M PCI-Express 2 I/0
403 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
407 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\
411 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
414 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
417 * BAT5 128K Cacheable, non-guarded
418 * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory)
420 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\
423 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\
427 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
428 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
431 * BAT6 256M Cache-inhibited, guarded
432 * 0xf000_0000 256M FLASH
434 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\
438 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\
442 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\
445 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
447 /* Map the last 1M of flash where we're running from reset */
448 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
452 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE |\
456 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
459 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
462 * BAT7 64M Cache-inhibited, guarded
463 * 0xe800_0000 64K NAND FLASH
464 * 0xe804_0000 128K DUART Registers
466 #define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\
470 #define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\
474 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\
477 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
480 * Miscellaneous configurable options
482 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
483 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
484 #define CONFIG_PREBOOT /* enable preboot variable */
485 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
488 * For booting Linux, the board info and command line data
489 * have to be in the first 16 MB of memory, since this is
490 * the maximum mapped by the Linux kernel during initialization.
492 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
493 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
496 * Environment Configuration
498 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
499 #define CONFIG_ENV_SIZE 0x8000
500 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
504 * fffc0000 - ffffffff Pri FDT (256KB)
505 * fff80000 - fffbffff Pri U-Boot Environment (256 KB)
506 * fff00000 - fff7ffff Pri U-Boot (512 KB)
507 * fef00000 - ffefffff Pri OS image (16MB)
508 * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
510 * f7fc0000 - f7ffffff Sec FDT (256KB)
511 * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB)
512 * f7f00000 - f7f7ffff Sec U-Boot (512 KB)
513 * f6f00000 - f7efffff Sec OS image (16MB)
514 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
516 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff00000)
517 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f00000)
518 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfffc0000)
519 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7fc0000)
520 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
521 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
523 #define CONFIG_PROG_UBOOT1 \
524 "$download_cmd $loadaddr $ubootfile; " \
525 "if test $? -eq 0; then " \
526 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
527 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
528 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
529 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
530 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
531 "if test $? -ne 0; then " \
532 "echo PROGRAM FAILED; " \
534 "echo PROGRAM SUCCEEDED; " \
537 "echo DOWNLOAD FAILED; " \
540 #define CONFIG_PROG_UBOOT2 \
541 "$download_cmd $loadaddr $ubootfile; " \
542 "if test $? -eq 0; then " \
543 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
544 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
545 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
546 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
547 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
548 "if test $? -ne 0; then " \
549 "echo PROGRAM FAILED; " \
551 "echo PROGRAM SUCCEEDED; " \
554 "echo DOWNLOAD FAILED; " \
557 #define CONFIG_BOOT_OS_NET \
558 "$download_cmd $osaddr $osfile; " \
559 "if test $? -eq 0; then " \
560 "if test -n $fdtaddr; then " \
561 "$download_cmd $fdtaddr $fdtfile; " \
562 "if test $? -eq 0; then " \
563 "bootm $osaddr - $fdtaddr; " \
565 "echo FDT DOWNLOAD FAILED; " \
571 "echo OS DOWNLOAD FAILED; " \
574 #define CONFIG_PROG_OS1 \
575 "$download_cmd $osaddr $osfile; " \
576 "if test $? -eq 0; then " \
577 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
578 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
579 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
580 "if test $? -ne 0; then " \
581 "echo OS PROGRAM FAILED; " \
583 "echo OS PROGRAM SUCCEEDED; " \
586 "echo OS DOWNLOAD FAILED; " \
589 #define CONFIG_PROG_OS2 \
590 "$download_cmd $osaddr $osfile; " \
591 "if test $? -eq 0; then " \
592 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
593 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
594 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
595 "if test $? -ne 0; then " \
596 "echo OS PROGRAM FAILED; " \
598 "echo OS PROGRAM SUCCEEDED; " \
601 "echo OS DOWNLOAD FAILED; " \
604 #define CONFIG_PROG_FDT1 \
605 "$download_cmd $fdtaddr $fdtfile; " \
606 "if test $? -eq 0; then " \
607 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
608 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
609 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
610 "if test $? -ne 0; then " \
611 "echo FDT PROGRAM FAILED; " \
613 "echo FDT PROGRAM SUCCEEDED; " \
616 "echo FDT DOWNLOAD FAILED; " \
619 #define CONFIG_PROG_FDT2 \
620 "$download_cmd $fdtaddr $fdtfile; " \
621 "if test $? -eq 0; then " \
622 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
623 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
624 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
625 "if test $? -ne 0; then " \
626 "echo FDT PROGRAM FAILED; " \
628 "echo FDT PROGRAM SUCCEEDED; " \
631 "echo FDT DOWNLOAD FAILED; " \
634 #define CONFIG_EXTRA_ENV_SETTINGS \
636 "download_cmd=tftp\0" \
637 "console_args=console=ttyS0,115200\0" \
638 "root_args=root=/dev/nfs rw\0" \
639 "misc_args=ip=on\0" \
640 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
641 "bootfile=/home/user/file\0" \
642 "osfile=/home/user/board.uImage\0" \
643 "fdtfile=/home/user/board.dtb\0" \
644 "ubootfile=/home/user/u-boot.bin\0" \
645 "fdtaddr=0x1e00000\0" \
646 "osaddr=0x1000000\0" \
647 "loadaddr=0x1000000\0" \
648 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
649 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
650 "prog_os1="CONFIG_PROG_OS1"\0" \
651 "prog_os2="CONFIG_PROG_OS2"\0" \
652 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
653 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
654 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
655 "bootcmd_flash1=run set_bootargs; " \
656 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
657 "bootcmd_flash2=run set_bootargs; " \
658 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
659 "bootcmd=run bootcmd_flash1\0"
660 #endif /* __CONFIG_H */