ARM: configs: Add da850evm_nand to boot from NAND
[oweals/u-boot.git] / include / configs / xpedite517x.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2009 Extreme Engineering Solutions, Inc.
4  * Copyright 2007-2008 Freescale Semiconductor, Inc.
5  */
6
7 /*
8  * xpedite517x board configuration file
9  */
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12
13 /*
14  * High Level Configuration Options
15  */
16 #define CONFIG_SYS_BOARD_NAME   "XPedite5170"
17 #define CONFIG_SYS_FORM_3U_VPX  1
18 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
19 #define CONFIG_BAT_RW           1       /* Use common BAT rw code */
20 #define CONFIG_HIGH_BATS        1       /* High BATs supported and enabled */
21 #define CONFIG_ALTIVEC          1
22
23 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup */
24 #define CONFIG_PCIE1            1       /* PCIE controller 1 */
25 #define CONFIG_PCIE2            1       /* PCIE controller 2 */
26 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
27 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
28 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
29
30 /*
31  * DDR config
32  */
33 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
34 #define CONFIG_DDR_SPD
35 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
36 #define SPD_EEPROM_ADDRESS1             0x54    /* Both channels use the */
37 #define SPD_EEPROM_ADDRESS2             0x54    /* same SPD data         */
38 #define SPD_EEPROM_OFFSET               0x200   /* OFFSET of SPD in EEPROM */
39 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
40 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
41 #define CONFIG_DDR_ECC
42 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
43 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
44 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
45 #define CONFIG_VERY_BIG_RAM
46 #define CONFIG_SYS_MAX_DDR_BAT_SIZE     0x80000000      /* BAT mapping size */
47
48 /*
49  * virtual address to be used for temporary mappings.  There
50  * should be 128k free at this VA.
51  */
52 #define CONFIG_SYS_SCRATCH_VA   0xe0000000
53
54 #ifndef __ASSEMBLY__
55 extern unsigned long get_board_sys_clk(unsigned long dummy);
56 #endif
57
58 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /* sysclk for MPC86xx */
59
60 /*
61  * L2CR setup
62  */
63 #define CONFIG_SYS_L2
64 #define L2_INIT         0
65 #define L2_ENABLE       (L2CR_L2E)
66
67 /*
68  * Base addresses -- Note these are effective addresses where the
69  * actual resources get mapped (not physical addresses)
70  */
71 #define CONFIG_SYS_CCSRBAR              0xef000000      /* relocated CCSRBAR */
72 #define CONFIG_SYS_CCSRBAR_PHYS         CONFIG_SYS_CCSRBAR
73 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
74 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0x0
75 #define CONFIG_SYS_IMMR                 CONFIG_SYS_CCSRBAR
76
77 /*
78  * Diagnostics
79  */
80 #define CONFIG_SYS_MEMTEST_START        0x10000000
81 #define CONFIG_SYS_MEMTEST_END          0x20000000
82 #define CONFIG_POST                     (CONFIG_SYS_POST_MEMORY |\
83                                          CONFIG_SYS_POST_I2C)
84 /* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
85 #define I2C_ADDR_IGNORE_LIST            {0x50}
86
87 /*
88  * Memory map
89  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
90  * 0x8000_0000  0xbfff_ffff     PCIe1 Mem               1G non-cacheable
91  * 0xc000_0000  0xcfff_ffff     PCIe2 Mem               256M non-cacheable
92  * 0xe000_0000  0xe7ff_ffff     SRAM/SSRAM/L1 Cache     128M non-cacheable
93  * 0xe800_0000  0xe87f_ffff     PCIe1 IO                8M non-cacheable
94  * 0xe880_0000  0xe8ff_ffff     PCIe2 IO                8M non-cacheable
95  * 0xef00_0000  0xef0f_ffff     CCSR/IMMR               1M non-cacheable
96  * 0xef80_0000  0xef8f_ffff     NAND Flash              1M non-cacheable
97  * 0xf000_0000  0xf7ff_ffff     NOR Flash 2             128M non-cacheable
98  * 0xf800_0000  0xffff_ffff     NOR Flash 1             128M non-cacheable
99  */
100
101 #define CONFIG_SYS_LBC_LCRR             (LCRR_CLKDIV_4 | LCRR_EADC_3)
102
103 /*
104  * NAND flash configuration
105  */
106 #define CONFIG_SYS_NAND_BASE            0xef800000
107 #define CONFIG_SYS_NAND_BASE2           0xef840000      /* Unused at this time */
108 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
109 #define CONFIG_SYS_MAX_NAND_DEVICE      2
110 #define CONFIG_NAND_ACTL
111 #define CONFIG_SYS_NAND_ACTL_ALE        (1 << 14)       /* C_LA14 */
112 #define CONFIG_SYS_NAND_ACTL_CLE        (1 << 15)       /* C_LA15 */
113 #define CONFIG_SYS_NAND_ACTL_NCE        0               /* NCE not controlled by ADDR */
114 #define CONFIG_SYS_NAND_ACTL_DELAY      25
115 #define CONFIG_JFFS2_NAND
116
117 /*
118  * NOR flash configuration
119  */
120 #define CONFIG_SYS_FLASH_BASE           0xf8000000
121 #define CONFIG_SYS_FLASH_BASE2          0xf0000000
122 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
123 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
124 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
125 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
126 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
127 #define CONFIG_FLASH_CFI_DRIVER
128 #define CONFIG_SYS_FLASH_CFI
129 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
130 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST       { {0xfff00000, 0xc0000}, \
131                                                   {0xf7f00000, 0xc0000} }
132 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
133 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000      /* early monitor loc */
134
135 /*
136  * Chip select configuration
137  */
138 /* NOR Flash 0 on CS0 */
139 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE  |\
140                                  BR_PS_16               |\
141                                  BR_V)
142 #define CONFIG_SYS_OR0_PRELIM   (OR_AM_128MB            |\
143                                  OR_GPCM_CSNT           |\
144                                  OR_GPCM_XACS           |\
145                                  OR_GPCM_ACS_DIV2       |\
146                                  OR_GPCM_SCY_8          |\
147                                  OR_GPCM_TRLX           |\
148                                  OR_GPCM_EHTR           |\
149                                  OR_GPCM_EAD)
150
151 /* NOR Flash 1 on CS1 */
152 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FLASH_BASE2 |\
153                                  BR_PS_16               |\
154                                  BR_V)
155 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
156
157 /* NAND flash on CS2 */
158 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_NAND_BASE   |\
159                                  BR_PS_8                |\
160                                  BR_V)
161 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_256KB            |\
162                                  OR_GPCM_BCTLD          |\
163                                  OR_GPCM_CSNT           |\
164                                  OR_GPCM_ACS_DIV4       |\
165                                  OR_GPCM_SCY_4          |\
166                                  OR_GPCM_TRLX           |\
167                                  OR_GPCM_EHTR)
168
169 /* Optional NAND flash on CS3 */
170 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_NAND_BASE2  |\
171                                  BR_PS_8                |\
172                                  BR_V)
173 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
174
175 /*
176  * Use L1 as initial stack
177  */
178 #define CONFIG_SYS_INIT_RAM_LOCK        1
179 #define CONFIG_SYS_INIT_RAM_ADDR        0xe0000000
180 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
181
182 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
183 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
184
185 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 KB for Mon */
186 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
187
188 /*
189  * Serial Port
190  */
191 #define CONFIG_SYS_NS16550_SERIAL
192 #define CONFIG_SYS_NS16550_REG_SIZE     1
193 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
194 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
195 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
196 #define CONFIG_SYS_BAUDRATE_TABLE       \
197         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
198 #define CONFIG_LOADS_ECHO               1       /* echo on for serial download */
199 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
200
201 /*
202  * I2C
203  */
204 #define CONFIG_SYS_I2C
205 #define CONFIG_SYS_I2C_FSL
206 #define CONFIG_SYS_FSL_I2C_SPEED        100000
207 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
208 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
209 #define CONFIG_SYS_FSL_I2C2_SPEED       100000
210 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
211 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
212
213 /* PEX8518 slave I2C interface */
214 #define CONFIG_SYS_I2C_PEX8518_ADDR     0x70
215
216 /* I2C DS1631 temperature sensor */
217 #define CONFIG_SYS_I2C_LM90_ADDR        0x4c
218
219 /* I2C EEPROM - AT24C128B */
220 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x54
221 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
222 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6       /* 64 byte pages */
223 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* take up to 10 msec */
224
225 /* I2C RTC */
226 #define CONFIG_RTC_M41T11               1
227 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
228 #define CONFIG_SYS_M41T11_BASE_YEAR     2000
229
230 /* GPIO */
231 #define CONFIG_PCA953X
232 #define CONFIG_SYS_I2C_PCA953X_ADDR0    0x18
233 #define CONFIG_SYS_I2C_PCA953X_ADDR1    0x1c
234 #define CONFIG_SYS_I2C_PCA953X_ADDR2    0x1e
235 #define CONFIG_SYS_I2C_PCA953X_ADDR3    0x1f
236 #define CONFIG_SYS_I2C_PCA953X_ADDR     CONFIG_SYS_I2C_PCA953X_ADDR0
237 #define CONFIG_SYS_I2C_PCA9553_ADDR     0x62
238
239 /*
240  * PU = pulled high, PD = pulled low
241  * I = input, O = output, IO = input/output
242  */
243 /* PCA9557 @ 0x18*/
244 #define CONFIG_SYS_PCA953X_C0_SER0_EN           0x01 /* PU; UART0 enable (1: enabled) */
245 #define CONFIG_SYS_PCA953X_C0_SER0_MODE         0x02 /* PU; UART0 serial mode select */
246 #define CONFIG_SYS_PCA953X_C0_SER1_EN           0x04 /* PU; UART1 enable (1: enabled) */
247 #define CONFIG_SYS_PCA953X_C0_SER1_MODE         0x08 /* PU; UART1 serial mode select */
248 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS     0x10 /* PU; Boot flash CS select */
249 #define CONFIG_SYS_PCA953X_NVM_WP               0x20 /* PU; Set to 0 to enable NVM writing */
250
251 /* PCA9557 @ 0x1c*/
252 #define CONFIG_SYS_PCA953X_XMC0_ROOT0           0x01 /* PU; Low if XMC is RC */
253 #define CONFIG_SYS_PCA953X_PLUG_GPIO0           0x02 /* Samtec connector GPIO */
254 #define CONFIG_SYS_PCA953X_XMC0_WAKE            0x04 /* PU; XMC wake */
255 #define CONFIG_SYS_PCA953X_XMC0_BIST            0x08 /* PU; XMC built in self test */
256 #define CONFIG_SYS_PCA953X_XMC_PRESENT          0x10 /* PU; Low if XMC module installed */
257 #define CONFIG_SYS_PCA953X_PMC_PRESENT          0x20 /* PU; Low if PMC module installed */
258 #define CONFIG_SYS_PCA953X_PMC0_MONARCH         0x40 /* PMC monarch mode enable */
259 #define CONFIG_SYS_PCA953X_PMC0_EREADY          0x80 /* PU; PMC PCI eready */
260
261 /* PCA9557 @ 0x1e*/
262 #define CONFIG_SYS_PCA953X_P0_GA0               0x01 /* PU; VPX Geographical address */
263 #define CONFIG_SYS_PCA953X_P0_GA1               0x02 /* PU; VPX Geographical address */
264 #define CONFIG_SYS_PCA953X_P0_GA2               0x04 /* PU; VPX Geographical address */
265 #define CONFIG_SYS_PCA953X_P0_GA3               0x08 /* PU; VPX Geographical address */
266 #define CONFIG_SYS_PCA953X_P0_GA4               0x10 /* PU; VPX Geographical address */
267 #define CONFIG_SYS_PCA953X_P0_GAP               0x20 /* PU; VPX Geographical address parity */
268 #define CONFIG_SYS_PCA953X_P1_SYSEN             0x80 /* PU; VPX P1 SYSCON */
269
270 /* PCA9557 @ 0x1f */
271 #define CONFIG_SYS_PCA953X_VPX_GPIO0            0x01 /* PU; VPX P15 GPIO */
272 #define CONFIG_SYS_PCA953X_VPX_GPIO1            0x02 /* PU; VPX P15 GPIO */
273 #define CONFIG_SYS_PCA953X_VPX_GPIO2            0x04 /* PU; VPX P15 GPIO */
274 #define CONFIG_SYS_PCA953X_VPX_GPIO3            0x08 /* PU; VPX P15 GPIO */
275
276 /*
277  * General PCI
278  * Memory space is mapped 1-1, but I/O space must start from 0.
279  */
280 /* PCIE1 - PEX8518 */
281 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
282 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BUS
283 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x40000000      /* 1G */
284 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
285 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe8000000
286 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
287
288 /* PCIE2 - VPX P1 */
289 #define CONFIG_SYS_PCIE2_MEM_BUS        0xc0000000
290 #define CONFIG_SYS_PCIE2_MEM_PHYS       CONFIG_SYS_PCIE2_MEM_BUS
291 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
292 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
293 #define CONFIG_SYS_PCIE2_IO_PHYS        0xe8800000
294 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000      /* 8M */
295
296 /*
297  * Networking options
298  */
299 #define CONFIG_ETHPRIME         "eTSEC1"
300
301 #define CONFIG_TSEC1            1
302 #define CONFIG_TSEC1_NAME       "eTSEC1"
303 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
304 #define TSEC1_PHY_ADDR          1
305 #define TSEC1_PHYIDX            0
306 #define CONFIG_HAS_ETH0
307
308 #define CONFIG_TSEC2            1
309 #define CONFIG_TSEC2_NAME       "eTSEC2"
310 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
311 #define TSEC2_PHY_ADDR          2
312 #define TSEC2_PHYIDX            0
313 #define CONFIG_HAS_ETH1
314
315 /*
316  * BAT mappings
317  */
318 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
319 #define CONFIG_SYS_CCSR_DEFAULT_DBATL   (CONFIG_SYS_CCSRBAR_DEFAULT     |\
320                                          BATL_PP_RW                     |\
321                                          BATL_CACHEINHIBIT              |\
322                                          BATL_GUARDEDSTORAGE)
323 #define CONFIG_SYS_CCSR_DEFAULT_DBATU   (CONFIG_SYS_CCSRBAR_DEFAULT     |\
324                                          BATU_BL_1M                     |\
325                                          BATU_VS                        |\
326                                          BATU_VP)
327 #define CONFIG_SYS_CCSR_DEFAULT_IBATL   (CONFIG_SYS_CCSRBAR_DEFAULT     |\
328                                          BATL_PP_RW                     |\
329                                          BATL_CACHEINHIBIT)
330 #define CONFIG_SYS_CCSR_DEFAULT_IBATU   CONFIG_SYS_CCSR_DEFAULT_DBATU
331 #endif
332
333 /*
334  * BAT0         2G      Cacheable, non-guarded
335  * 0x0000_0000  2G      DDR
336  */
337 #define CONFIG_SYS_DBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
338 #define CONFIG_SYS_DBAT0U       (BATU_BL_2G | BATU_VS | BATU_VP)
339 #define CONFIG_SYS_IBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
340 #define CONFIG_SYS_IBAT0U       CONFIG_SYS_DBAT0U
341
342 /*
343  * BAT1         1G      Cache-inhibited, guarded
344  * 0x8000_0000  1G      PCI-Express 1 Memory
345  */
346 #define CONFIG_SYS_DBAT1L       (CONFIG_SYS_PCIE1_MEM_PHYS      |\
347                                  BATL_PP_RW                     |\
348                                  BATL_CACHEINHIBIT              |\
349                                  BATL_GUARDEDSTORAGE)
350 #define CONFIG_SYS_DBAT1U       (CONFIG_SYS_PCIE1_MEM_PHYS      |\
351                                  BATU_BL_1G                     |\
352                                  BATU_VS                        |\
353                                  BATU_VP)
354 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCIE1_MEM_PHYS      |\
355                                  BATL_PP_RW                     |\
356                                  BATL_CACHEINHIBIT)
357 #define CONFIG_SYS_IBAT1U       CONFIG_SYS_DBAT1U
358
359 /*
360  * BAT2         512M    Cache-inhibited, guarded
361  * 0xc000_0000  512M    PCI-Express 2 Memory
362  */
363 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_PCIE2_MEM_PHYS      |\
364                                  BATL_PP_RW                     |\
365                                  BATL_CACHEINHIBIT              |\
366                                  BATL_GUARDEDSTORAGE)
367 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_PCIE2_MEM_PHYS      |\
368                                  BATU_BL_512M                   |\
369                                  BATU_VS                        |\
370                                  BATU_VP)
371 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCIE2_MEM_PHYS      |\
372                                  BATL_PP_RW                     |\
373                                  BATL_CACHEINHIBIT)
374 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
375
376 /*
377  * BAT3         1M      Cache-inhibited, guarded
378  * 0xe000_0000  1M      CCSR
379  */
380 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_CCSRBAR             |\
381                                  BATL_PP_RW                     |\
382                                  BATL_CACHEINHIBIT              |\
383                                  BATL_GUARDEDSTORAGE)
384 #define CONFIG_SYS_DBAT3U       (CONFIG_SYS_CCSRBAR             |\
385                                  BATU_BL_1M                     |\
386                                  BATU_VS                        |\
387                                  BATU_VP)
388 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_CCSRBAR             |\
389                                  BATL_PP_RW                     |\
390                                  BATL_CACHEINHIBIT)
391 #define CONFIG_SYS_IBAT3U       CONFIG_SYS_DBAT3U
392
393 /*
394  * BAT4         32M     Cache-inhibited, guarded
395  * 0xe200_0000  16M     PCI-Express 1 I/O
396  * 0xe300_0000  16M     PCI-Express 2 I/0
397  */
398 #define CONFIG_SYS_DBAT4L       (CONFIG_SYS_PCIE1_IO_PHYS       |\
399                                  BATL_PP_RW                     |\
400                                  BATL_CACHEINHIBIT              |\
401                                  BATL_GUARDEDSTORAGE)
402 #define CONFIG_SYS_DBAT4U       (CONFIG_SYS_PCIE1_IO_PHYS       |\
403                                  BATU_BL_32M                    |\
404                                  BATU_VS                        |\
405                                  BATU_VP)
406 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCIE1_IO_PHYS       |\
407                                  BATL_PP_RW                     |\
408                                  BATL_CACHEINHIBIT)
409 #define CONFIG_SYS_IBAT4U       CONFIG_SYS_DBAT4U
410
411 /*
412  * BAT5         128K    Cacheable, non-guarded
413  * 0xe400_1000  128K    Init RAM for stack in the CPU DCache (no backing memory)
414  */
415 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_INIT_RAM_ADDR       |\
416                                  BATL_PP_RW                     |\
417                                  BATL_MEMCOHERENCE)
418 #define CONFIG_SYS_DBAT5U       (CONFIG_SYS_INIT_RAM_ADDR       |\
419                                  BATU_BL_128K                   |\
420                                  BATU_VS                        |\
421                                  BATU_VP)
422 #define CONFIG_SYS_IBAT5L       CONFIG_SYS_DBAT5L
423 #define CONFIG_SYS_IBAT5U       CONFIG_SYS_DBAT5U
424
425 /*
426  * BAT6         256M    Cache-inhibited, guarded
427  * 0xf000_0000  256M    FLASH
428  */
429 #define CONFIG_SYS_DBAT6L       (CONFIG_SYS_FLASH_BASE2         |\
430                                  BATL_PP_RW                     |\
431                                  BATL_CACHEINHIBIT              |\
432                                  BATL_GUARDEDSTORAGE)
433 #define CONFIG_SYS_DBAT6U       (CONFIG_SYS_FLASH_BASE          |\
434                                  BATU_BL_256M                   |\
435                                  BATU_VS                        |\
436                                  BATU_VP)
437 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_FLASH_BASE          |\
438                                  BATL_PP_RW                     |\
439                                  BATL_MEMCOHERENCE)
440 #define CONFIG_SYS_IBAT6U       CONFIG_SYS_DBAT6U
441
442 /* Map the last 1M of flash where we're running from reset */
443 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY  |\
444                                  BATL_PP_RW                     |\
445                                  BATL_CACHEINHIBIT              |\
446                                  BATL_GUARDEDSTORAGE)
447 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE                   |\
448                                  BATU_BL_1M                     |\
449                                  BATU_VS                        |\
450                                  BATU_VP)
451 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY  |\
452                                  BATL_PP_RW                     |\
453                                  BATL_MEMCOHERENCE)
454 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
455
456 /*
457  * BAT7         64M     Cache-inhibited, guarded
458  * 0xe800_0000  64K     NAND FLASH
459  * 0xe804_0000  128K    DUART Registers
460  */
461 #define CONFIG_SYS_DBAT7L       (CONFIG_SYS_NAND_BASE           |\
462                                  BATL_PP_RW                     |\
463                                  BATL_CACHEINHIBIT              |\
464                                  BATL_GUARDEDSTORAGE)
465 #define CONFIG_SYS_DBAT7U       (CONFIG_SYS_NAND_BASE           |\
466                                  BATU_BL_512K                   |\
467                                  BATU_VS                        |\
468                                  BATU_VP)
469 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_NAND_BASE           |\
470                                  BATL_PP_RW                     |\
471                                  BATL_CACHEINHIBIT)
472 #define CONFIG_SYS_IBAT7U       CONFIG_SYS_DBAT7U
473
474 /*
475  * Miscellaneous configurable options
476  */
477 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
478 #define CONFIG_LOADADDR         0x1000000       /* default location for tftp and bootm */
479 #define CONFIG_PREBOOT                          /* enable preboot variable */
480 #define CONFIG_INTEGRITY                        /* support booting INTEGRITY OS */
481
482 /*
483  * For booting Linux, the board info and command line data
484  * have to be in the first 16 MB of memory, since this is
485  * the maximum mapped by the Linux kernel during initialization.
486  */
487 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)      /* Initial Memory map for Linux*/
488 #define CONFIG_SYS_BOOTM_LEN    (16 << 20)      /* Increase max gunzip size */
489
490 /*
491  * Environment Configuration
492  */
493 #define CONFIG_ENV_SECT_SIZE    0x20000         /* 128k (one sector) for env */
494 #define CONFIG_ENV_SIZE         0x8000
495 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
496
497 /*
498  * Flash memory map:
499  * fffc0000 - ffffffff  Pri FDT (256KB)
500  * fff80000 - fffbffff  Pri U-Boot Environment (256 KB)
501  * fff00000 - fff7ffff  Pri U-Boot (512 KB)
502  * fef00000 - ffefffff  Pri OS image (16MB)
503  * f8000000 - feefffff  Pri OS Use/Filesystem (111MB)
504  *
505  * f7fc0000 - f7ffffff  Sec FDT (256KB)
506  * f7f80000 - f7fbffff  Sec U-Boot Environment (256 KB)
507  * f7f00000 - f7f7ffff  Sec U-Boot (512 KB)
508  * f6f00000 - f7efffff  Sec OS image (16MB)
509  * f0000000 - f6efffff  Sec OS Use/Filesystem (111MB)
510  */
511 #define CONFIG_UBOOT1_ENV_ADDR  __stringify(0xfff00000)
512 #define CONFIG_UBOOT2_ENV_ADDR  __stringify(0xf7f00000)
513 #define CONFIG_FDT1_ENV_ADDR    __stringify(0xfffc0000)
514 #define CONFIG_FDT2_ENV_ADDR    __stringify(0xf7fc0000)
515 #define CONFIG_OS1_ENV_ADDR     __stringify(0xfef00000)
516 #define CONFIG_OS2_ENV_ADDR     __stringify(0xf6f00000)
517
518 #define CONFIG_PROG_UBOOT1                                              \
519         "$download_cmd $loadaddr $ubootfile; "                          \
520         "if test $? -eq 0; then "                                       \
521                 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "         \
522                 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "               \
523                 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "       \
524                 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "          \
525                 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "      \
526                 "if test $? -ne 0; then "                               \
527                         "echo PROGRAM FAILED; "                         \
528                 "else; "                                                \
529                         "echo PROGRAM SUCCEEDED; "                      \
530                 "fi; "                                                  \
531         "else; "                                                        \
532                 "echo DOWNLOAD FAILED; "                                \
533         "fi;"
534
535 #define CONFIG_PROG_UBOOT2                                              \
536         "$download_cmd $loadaddr $ubootfile; "                          \
537         "if test $? -eq 0; then "                                       \
538                 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "         \
539                 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "               \
540                 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "       \
541                 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "          \
542                 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "      \
543                 "if test $? -ne 0; then "                               \
544                         "echo PROGRAM FAILED; "                         \
545                 "else; "                                                \
546                         "echo PROGRAM SUCCEEDED; "                      \
547                 "fi; "                                                  \
548         "else; "                                                        \
549                 "echo DOWNLOAD FAILED; "                                \
550         "fi;"
551
552 #define CONFIG_BOOT_OS_NET                                              \
553         "$download_cmd $osaddr $osfile; "                               \
554         "if test $? -eq 0; then "                                       \
555                 "if test -n $fdtaddr; then "                            \
556                         "$download_cmd $fdtaddr $fdtfile; "             \
557                         "if test $? -eq 0; then "                       \
558                                 "bootm $osaddr - $fdtaddr; "            \
559                         "else; "                                        \
560                                 "echo FDT DOWNLOAD FAILED; "            \
561                         "fi; "                                          \
562                 "else; "                                                \
563                         "bootm $osaddr; "                               \
564                 "fi; "                                                  \
565         "else; "                                                        \
566                 "echo OS DOWNLOAD FAILED; "                             \
567         "fi;"
568
569 #define CONFIG_PROG_OS1                                                 \
570         "$download_cmd $osaddr $osfile; "                               \
571         "if test $? -eq 0; then "                                       \
572                 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; "              \
573                 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "        \
574                 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "       \
575                 "if test $? -ne 0; then "                               \
576                         "echo OS PROGRAM FAILED; "                      \
577                 "else; "                                                \
578                         "echo OS PROGRAM SUCCEEDED; "                   \
579                 "fi; "                                                  \
580         "else; "                                                        \
581                 "echo OS DOWNLOAD FAILED; "                             \
582         "fi;"
583
584 #define CONFIG_PROG_OS2                                                 \
585         "$download_cmd $osaddr $osfile; "                               \
586         "if test $? -eq 0; then "                                       \
587                 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; "              \
588                 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "        \
589                 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "       \
590                 "if test $? -ne 0; then "                               \
591                         "echo OS PROGRAM FAILED; "                      \
592                 "else; "                                                \
593                         "echo OS PROGRAM SUCCEEDED; "                   \
594                 "fi; "                                                  \
595         "else; "                                                        \
596                 "echo OS DOWNLOAD FAILED; "                             \
597         "fi;"
598
599 #define CONFIG_PROG_FDT1                                                \
600         "$download_cmd $fdtaddr $fdtfile; "                             \
601         "if test $? -eq 0; then "                                       \
602                 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"              \
603                 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "      \
604                 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "     \
605                 "if test $? -ne 0; then "                               \
606                         "echo FDT PROGRAM FAILED; "                     \
607                 "else; "                                                \
608                         "echo FDT PROGRAM SUCCEEDED; "                  \
609                 "fi; "                                                  \
610         "else; "                                                        \
611                 "echo FDT DOWNLOAD FAILED; "                            \
612         "fi;"
613
614 #define CONFIG_PROG_FDT2                                                \
615         "$download_cmd $fdtaddr $fdtfile; "                             \
616         "if test $? -eq 0; then "                                       \
617                 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"              \
618                 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "      \
619                 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "     \
620                 "if test $? -ne 0; then "                               \
621                         "echo FDT PROGRAM FAILED; "                     \
622                 "else; "                                                \
623                         "echo FDT PROGRAM SUCCEEDED; "                  \
624                 "fi; "                                                  \
625         "else; "                                                        \
626                 "echo FDT DOWNLOAD FAILED; "                            \
627         "fi;"
628
629 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
630         "autoload=yes\0"                                                \
631         "download_cmd=tftp\0"                                           \
632         "console_args=console=ttyS0,115200\0"                           \
633         "root_args=root=/dev/nfs rw\0"                                  \
634         "misc_args=ip=on\0"                                             \
635         "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
636         "bootfile=/home/user/file\0"                                    \
637         "osfile=/home/user/board.uImage\0"                              \
638         "fdtfile=/home/user/board.dtb\0"                                \
639         "ubootfile=/home/user/u-boot.bin\0"                             \
640         "fdtaddr=0x1e00000\0"                                           \
641         "osaddr=0x1000000\0"                                            \
642         "loadaddr=0x1000000\0"                                          \
643         "prog_uboot1="CONFIG_PROG_UBOOT1"\0"                            \
644         "prog_uboot2="CONFIG_PROG_UBOOT2"\0"                            \
645         "prog_os1="CONFIG_PROG_OS1"\0"                                  \
646         "prog_os2="CONFIG_PROG_OS2"\0"                                  \
647         "prog_fdt1="CONFIG_PROG_FDT1"\0"                                \
648         "prog_fdt2="CONFIG_PROG_FDT2"\0"                                \
649         "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"          \
650         "bootcmd_flash1=run set_bootargs; "                             \
651                 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
652         "bootcmd_flash2=run set_bootargs; "                             \
653                 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
654         "bootcmd=run bootcmd_flash1\0"
655 #endif  /* __CONFIG_H */