3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * High Level Configuration Options
35 #define CONFIG_PXA250 1 /* This is an PXA250 CPU */
36 #define CONFIG_XM250 1 /* on a MicroSys XM250 Board */
37 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
40 * Size of malloc() pool; this lives below the uppermost 128 KiB which are
41 * used for the RAM copy of the uboot code
44 #define CFG_MALLOC_LEN (256*1024)
45 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
50 #define CONFIG_DRIVER_SMC91111
51 #define CONFIG_SMC91111_BASE 0x04000300
52 #undef CONFIG_SMC91111_EXT_PHY
53 #define CONFIG_SMC_USE_32_BIT
54 #undef CONFIG_SHOW_ACTIVITY
55 #define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
60 #define CONFIG_HARD_I2C 1
61 #define CFG_I2C_SPEED 50000
62 #define CFG_I2C_SLAVE 0xfe
64 #define CONFIG_RTC_PCF8563 1
65 #define CFG_I2C_RTC_ADDR 0x51
67 #define CFG_I2C_EEPROM_ADDR 0x58 /* A0 = 0 (hardwired) */
68 #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 4 bits = 16 octets */
69 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* between stop and start */
70 #define CFG_I2C_EEPROM_ADDR_LEN 1 /* length of address */
71 #define CFG_EEPROM_SIZE 2048 /* size in bytes */
72 #undef CFG_I2C_INIT_BOARD /* board has no own init */
75 * select serial console configuration
77 #define CONFIG_FFUART 1 /* we use FFUART */
79 /* allow to overwrite serial and ethaddr */
80 #define CONFIG_ENV_OVERWRITE
82 #define CONFIG_BAUDRATE 115200
86 * Command line configuration.
88 #include <config_cmd_default.h>
90 #define CONFIG_CMD_ELF
91 #define CONFIG_CMD_EEPROM
92 #define CONFIG_CMD_DATE
93 #define CONFIG_CMD_I2C
96 #define CONFIG_BOOTDELAY 3
99 * Miscellaneous configurable options
101 #define CFG_LONGHELP /* undef to save memory */
102 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
103 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
104 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
105 #define CFG_MAXARGS 16 /* max number of command args */
106 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
108 #define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
109 #define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
111 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
113 #define CFG_LOAD_ADDR 0xa3000000 /* default load address */
115 #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
116 #define CFG_CPUSPEED 0x161 /* set core clock to 400/400/100 MHz */
118 /* valid baudrates */
120 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
123 * Definitions related to passing arguments to kernel.
125 #define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
126 #define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
127 #define CONFIG_INITRD_TAG 1 /* do not send initrd params */
128 #undef CONFIG_VFD /* do not send framebuffer setup */
133 * The stack sizes are set up in start.S using the settings below
135 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
136 #ifdef CONFIG_USE_IRQ
137 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
138 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
142 * Physical Memory Map
144 #define CONFIG_NR_DRAM_BANKS 4
145 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
146 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
147 #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
148 #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
149 #define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
150 #define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
151 #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
152 #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
154 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
155 #define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */
156 #define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
157 #define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */
158 #define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
160 #define CFG_DRAM_BASE 0xa0000000
161 #define CFG_DRAM_SIZE 0x04000000
163 #define CFG_FLASH_BASE PHYS_FLASH_1
166 * FLASH and environment organization
168 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
169 #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
171 /* timeout values are in ticks */
172 #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
173 #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
174 #define CFG_FLASH_LOCK_TOUT (2*CFG_HZ) /* Timeout for Flash Set Lock Bit */
175 #define CFG_FLASH_UNLOCK_TOUT (2*CFG_HZ) /* Timeout for Flash Clear Lock Bits */
176 #define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
178 #define CFG_ENV_IS_IN_FLASH 1
179 #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector */
180 #define CFG_ENV_SIZE 0x4000
181 #define CFG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */
182 #define CFG_MONITOR_LEN 0x20000 /* 128 KiB */
184 /******************************************************************************
186 * CPU specific defines
188 ******************************************************************************/
193 * GPIO pin assignments
194 * GPIO Name Dir Out AF
217 * 22 PGMEN O 1 FIXME for debug only enable flash
237 * 42 RS232FOFF O 0 00
277 * NOTE: All NC's are defined to be outputs
280 /* Pin direction control */
281 #define CFG_GPDR0_VAL 0xd3808000
282 #define CFG_GPDR1_VAL 0xfcffab83
283 #define CFG_GPDR2_VAL 0x0001ffff
284 /* Set and Clear registers */
285 #define CFG_GPSR0_VAL 0x00008000
286 #define CFG_GPSR1_VAL 0x00ff0002
287 #define CFG_GPSR2_VAL 0x0001c000
288 #define CFG_GPCR0_VAL 0x00000000
289 #define CFG_GPCR1_VAL 0x00000000
290 #define CFG_GPCR2_VAL 0x00000000
291 /* Edge detect registers (these are set by the kernel) */
292 #define CFG_GRER0_VAL 0x00002180
293 #define CFG_GRER1_VAL 0x00000000
294 #define CFG_GRER2_VAL 0x00000000
295 #define CFG_GFER0_VAL 0x000043e0
296 #define CFG_GFER1_VAL 0x00000000
297 #define CFG_GFER2_VAL 0x00000000
298 /* Alternate function registers */
299 #define CFG_GAFR0_L_VAL 0x80000004
300 #define CFG_GAFR0_U_VAL 0x595a8010
301 #define CFG_GAFR1_L_VAL 0x699a9559
302 #define CFG_GAFR1_U_VAL 0xaaa5aaaa
303 #define CFG_GAFR2_L_VAL 0xaaaaaaaa
304 #define CFG_GAFR2_U_VAL 0x00000002
307 * Clocks, power control and interrupts
309 #define CFG_PSSR_VAL 0x00000030
310 #define CFG_CCCR_VAL 0x00000161 /* 100 MHz memory, 400 MHz CPU, 400 Turbo */
311 #define CFG_CKEN_VAL 0x000141ec /* FFUART and STUART enabled */
312 #define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */
325 #define CFG_MSC0_VAL 0x122423f0 /* FLASH / LAN (cs0)/(cS1) */
326 #define CFG_MSC1_VAL 0x35f4aa4c /* USB / ST3+ST5 (cs2)/(cS3) */
327 #define CFG_MSC2_VAL 0x35f435fc /* IDE / BCR + WatchDog (cs4)/(cS5) */
328 #define CFG_MDCNFG_VAL 0x000009c9
329 #define CFG_MDMRS_VAL 0x00220022
330 #define CFG_MDREFR_VAL 0x000da018 /* Initial setting, individual bits set in lowlevel_init.S */
333 * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
335 #define CFG_MECR_VAL 0x00000000
336 #define CFG_MCMEM0_VAL 0x00010504
337 #define CFG_MCMEM1_VAL 0x00010504
338 #define CFG_MCATT0_VAL 0x00010504
339 #define CFG_MCATT1_VAL 0x00010504
340 #define CFG_MCIO0_VAL 0x00004715
341 #define CFG_MCIO1_VAL 0x00004715
343 /* Board specific defines */
347 /* global prototypes */
348 void led_code(int code, int color);
352 #endif /* __CONFIG_H */