1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the WB50N CPU Module.
9 #include <asm/hardware.h>
11 /* ARM asynchronous clock */
12 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768
13 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
15 #define CONFIG_ARCH_CPU_INIT
17 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
18 #define CONFIG_SETUP_MEMORY_TAGS
19 #define CONFIG_INITRD_TAG
21 #ifndef CONFIG_SPL_BUILD
22 #define CONFIG_SKIP_LOWLEVEL_INIT
25 /* general purpose I/O */
26 #define CONFIG_AT91_GPIO
29 #define CONFIG_ATMEL_USART
30 #define CONFIG_USART_BASE ATMEL_BASE_DBGU
31 #define CONFIG_USART_ID ATMEL_ID_DBGU
36 #define CONFIG_BOOTP_BOOTFILESIZE
39 #define CONFIG_NR_DRAM_BANKS 1
40 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
41 #define CONFIG_SYS_SDRAM_SIZE 0x04000000
43 #ifdef CONFIG_SPL_BUILD
44 #define CONFIG_SYS_INIT_SP_ADDR 0x310000
46 #define CONFIG_SYS_INIT_SP_ADDR \
47 (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
50 #define CONFIG_SYS_MEMTEST_START 0x21000000
51 #define CONFIG_SYS_MEMTEST_END 0x22000000
54 #define CONFIG_SYS_MAX_NAND_DEVICE 1
55 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
57 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
59 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
60 #define CONFIG_SYS_NAND_ONFI_DETECTION
61 /* PMECC & PMERRLOC */
62 #define CONFIG_ATMEL_NAND_HWECC
63 #define CONFIG_ATMEL_NAND_HW_PMECC
64 #define CONFIG_PMECC_CAP 8
65 #define CONFIG_PMECC_SECTOR_SIZE 512
67 /* Ethernet Hardware */
70 #define CONFIG_NET_RETRY_COUNT 20
71 #define CONFIG_MACB_SEARCH_PHY
73 #define CONFIG_ETHADDR C0:EE:40:00:00:00
74 #define CONFIG_ENV_OVERWRITE 1
76 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
78 #define CONFIG_EXTRA_ENV_SETTINGS \
82 /* bootstrap + u-boot + env in nandflash */
83 #define CONFIG_ENV_OFFSET 0xA0000
84 #define CONFIG_ENV_OFFSET_REDUND 0xC0000
85 #define CONFIG_ENV_SIZE 0x20000
86 #define CONFIG_BOOTCOMMAND \
87 "nand read 0x22000000 0x000e0000 0x500000; " \
90 #define CONFIG_BOOTARGS \
91 "rw rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
93 #define CONFIG_BAUDRATE 115200
95 #define CONFIG_SYS_CBSIZE 1024
96 #define CONFIG_SYS_MAXARGS 16
97 #define CONFIG_SYS_PBSIZE \
98 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
100 /* Size of malloc() pool */
101 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
104 #define CONFIG_SPL_TEXT_BASE 0x300000
105 #define CONFIG_SPL_MAX_SIZE 0x10000
106 #define CONFIG_SPL_BSS_START_ADDR 0x20000000
107 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
108 #define CONFIG_SYS_SPL_MALLOC_START 0x20080000
109 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
111 #define CONFIG_SYS_MONITOR_LEN (512 << 10)
113 #define CONFIG_SPL_NAND_DRIVERS
114 #define CONFIG_SPL_NAND_BASE
115 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
116 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
117 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800
118 #define CONFIG_SYS_NAND_PAGE_COUNT 64
119 #define CONFIG_SYS_NAND_OOBSIZE 64
120 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
121 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
122 #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER