include/configs/vme8349.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * esd vme8349 U-Boot configuration file
   4  * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
   5  *
   6  * (C) Copyright 2006-2010
   7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8  *
   9  * reinhard.arlt@esd-electronics.de
  10  * Based on the MPC8349EMDS config.
  11  */
  12
  13 /*
  14  * vme8349 board configuration file.
  15  */
  16
  17 #ifndef __CONFIG_H
  18 #define __CONFIG_H
  19
  20 /*
  21  * Top level Makefile configuration choices
  22  */
  23 #ifdef CONFIG_CADDY2
  24 #define VME_CADDY2
  25 #endif
  26
  27 /*
  28  * High Level Configuration Options
  29  */
  30 #define CONFIG_E300             1       /* E300 Family */
  31 #define CONFIG_MPC834x          1       /* MPC834x family */
  32 #define CONFIG_MPC8349          1       /* MPC8349 specific */
  33 #define CONFIG_VME8349          1       /* ESD VME8349 board specific */
  34
  35 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
  36 #undef CONFIG_MPC83XX_PCI2              /* support for 2nd PCI controller */
  37
  38 #define CONFIG_PCI_66M
  39 #ifdef CONFIG_PCI_66M
  40 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
  41 #else
  42 #define CONFIG_83XX_CLKIN       33000000        /* in Hz */
  43 #endif
  44
  45 #ifndef CONFIG_SYS_CLK_FREQ
  46 #ifdef CONFIG_PCI_66M
  47 #define CONFIG_SYS_CLK_FREQ     66000000
  48 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_4X1
  49 #else
  50 #define CONFIG_SYS_CLK_FREQ     33000000
  51 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_8X1
  52 #endif
  53 #endif
  54
  55 #define CONFIG_SYS_IMMR         0xE0000000
  56
  57 #undef CONFIG_SYS_DRAM_TEST                     /* memory test, takes time */
  58 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  59 #define CONFIG_SYS_MEMTEST_END          0x00100000
  60
  61 /*
  62  * DDR Setup
  63  */
  64 #define CONFIG_DDR_ECC                  /* only for ECC DDR module */
  65 #define CONFIG_DDR_ECC_CMD              /* use DDR ECC user commands */
  66 #define CONFIG_SPD_EEPROM
  67 #define SPD_EEPROM_ADDRESS              0x54
  68 #define CONFIG_SYS_READ_SPD             vme8349_read_spd
  69 #define CONFIG_SYS_83XX_DDR_USES_CS0    /* esd; Fsl board uses CS2/CS3 */
  70
  71 /*
  72  * 32-bit data path mode.
  73  *
  74  * Please note that using this mode for devices with the real density of 64-bit
  75  * effectively reduces the amount of available memory due to the effect of
  76  * wrapping around while translating address to row/columns, for example in the
  77  * 256MB module the upper 128MB get aliased with contents of the lower
  78  * 128MB); normally this define should be used for devices with real 32-bit
  79  * data path.
  80  */
  81 #undef CONFIG_DDR_32BIT
  82
  83 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is sys memory*/
  84 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  85 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  86 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
  87                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  88 #define CONFIG_DDR_2T_TIMING
  89 #define CONFIG_SYS_DDRCDR               (DDRCDR_DHC_EN \
  90                                         | DDRCDR_ODT \
  91                                         | DDRCDR_Q_DRN)
  92                                         /* 0x80080001 */
  93
  94 /*
  95  * FLASH on the Local Bus
  96  */
  97 #define CONFIG_SYS_FLASH_CFI
  98 #define CONFIG_FLASH_CFI_DRIVER                         /* use the CFI driver */
  99 #ifdef VME_CADDY2
 100 #define CONFIG_SYS_FLASH_BASE           0xffc00000      /* start of FLASH   */
 101 #define CONFIG_SYS_FLASH_SIZE           4               /* flash size in MB */
 102 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | \
 103                                          BR_PS_16 |     /*  16bit */ \
 104                                          BR_MS_GPCM |   /*  MSEL = GPCM */ \
 105                                          BR_V)          /* valid */
 106
 107 #define CONFIG_SYS_OR0_PRELIM           (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 108                                         | OR_GPCM_XAM \
 109                                         | OR_GPCM_CSNT \
 110                                         | OR_GPCM_ACS_DIV2 \
 111                                         | OR_GPCM_XACS \
 112                                         | OR_GPCM_SCY_15 \
 113                                         | OR_GPCM_TRLX_SET \
 114                                         | OR_GPCM_EHTR_SET \
 115                                         | OR_GPCM_EAD)
 116                                         /* 0xffc06ff7 */
 117 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 118 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_4MB)
 119 #else
 120 #define CONFIG_SYS_FLASH_BASE           0xf8000000      /* start of FLASH   */
 121 #define CONFIG_SYS_FLASH_SIZE           128             /* flash size in MB */
 122 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | \
 123                                          BR_PS_16 |     /*  16bit */ \
 124                                          BR_MS_GPCM |   /*  MSEL = GPCM */ \
 125                                          BR_V)          /* valid */
 126
 127 #define CONFIG_SYS_OR0_PRELIM           (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 128                                         | OR_GPCM_XAM \
 129                                         | OR_GPCM_CSNT \
 130                                         | OR_GPCM_ACS_DIV2 \
 131                                         | OR_GPCM_XACS \
 132                                         | OR_GPCM_SCY_15 \
 133                                         | OR_GPCM_TRLX_SET \
 134                                         | OR_GPCM_EHTR_SET \
 135                                         | OR_GPCM_EAD)
 136                                         /* 0xf8006ff7 */
 137 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 138 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_128MB)
 139 #endif
 140 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 141
 142 #define CONFIG_SYS_WINDOW1_BASE         0xf0000000
 143 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_WINDOW1_BASE \
 144                                         | BR_PS_32 \
 145                                         | BR_MS_GPCM \
 146                                         | BR_V)
 147                                         /* 0xF0001801 */
 148 #define CONFIG_SYS_OR1_PRELIM           (OR_AM_256KB \
 149                                         | OR_GPCM_SETA)
 150                                         /* 0xfffc0208 */
 151 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_WINDOW1_BASE
 152 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_256KB)
 153
 154 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 155 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device*/
 156
 157 #undef CONFIG_SYS_FLASH_CHECKSUM
 158 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase TO (ms) */
 159 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write TO (ms) */
 160
 161 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 162
 163 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 164 #define CONFIG_SYS_RAMBOOT
 165 #else
 166 #undef CONFIG_SYS_RAMBOOT
 167 #endif
 168
 169 #define CONFIG_SYS_INIT_RAM_LOCK        1
 170 #define CONFIG_SYS_INIT_RAM_ADDR        0xF7000000      /* Initial RAM addr */
 171 #define CONFIG_SYS_INIT_RAM_SIZE                0x1000          /* size */
 172
 173 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 174                                          GENERATED_GBL_DATA_SIZE)
 175 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 176
 177 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB */
 178 #define CONFIG_SYS_MALLOC_LEN           (256 * 1024)    /* Malloc size */
 179
 180 /*
 181  * Local Bus LCRR and LBCR regs
 182  *    LCRR:  no DLL bypass, Clock divider is 4
 183  * External Local Bus rate is
 184  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 185  */
 186 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 187 #define CONFIG_SYS_LBC_LBCR     0x00000000
 188
 189 #undef CONFIG_SYS_LB_SDRAM      /* if board has SDRAM on local bus */
 190
 191 /*
 192  * Serial Port
 193  */
 194 #define CONFIG_SYS_NS16550_SERIAL
 195 #define CONFIG_SYS_NS16550_REG_SIZE     1
 196 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 197
 198 #define CONFIG_SYS_BAUDRATE_TABLE  \
 199                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 200
 201 #define CONFIG_SYS_NS16550_COM1         (CONFIG_SYS_IMMR + 0x4500)
 202 #define CONFIG_SYS_NS16550_COM2         (CONFIG_SYS_IMMR + 0x4600)
 203
 204 /* I2C */
 205 #define CONFIG_SYS_I2C
 206 #define CONFIG_SYS_I2C_FSL
 207 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 208 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 209 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 210 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 211 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 212 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 213 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 214 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
 215
 216 #define CONFIG_SYS_I2C_8574_ADDR2       0x20    /* I2C1, PCF8574 */
 217
 218 /* TSEC */
 219 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 220 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 221 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 222 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
 223
 224 /*
 225  * General PCI
 226  * Addresses are mapped 1-1.
 227  */
 228 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 229 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 230 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 231 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 232 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 233 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 234 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 235 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 236 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 237
 238 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 239 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 240 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 241 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 242 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 243 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 244 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 245 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 246 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 247
 248 #if defined(CONFIG_PCI)
 249
 250 #define PCI_64BIT
 251 #define PCI_ONE_PCI1
 252 #if defined(PCI_64BIT)
 253 #undef PCI_ALL_PCI1
 254 #undef PCI_TWO_PCI1
 255 #undef PCI_ONE_PCI1
 256 #endif
 257
 258 #undef CONFIG_EEPRO100
 259 #undef CONFIG_TULIP
 260
 261 #if !defined(CONFIG_PCI_PNP)
 262         #define PCI_ENET0_IOADDR        0xFIXME
 263         #define PCI_ENET0_MEMADDR       0xFIXME
 264         #define PCI_IDSEL_NUMBER        0xFIXME
 265 #endif
 266
 267 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 268 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 269
 270 #endif  /* CONFIG_PCI */
 271
 272 /*
 273  * TSEC configuration
 274  */
 275
 276 #if defined(CONFIG_TSEC_ENET)
 277
 278 #define CONFIG_GMII                     /* MII PHY management */
 279 #define CONFIG_TSEC1
 280 #define CONFIG_TSEC1_NAME       "TSEC0"
 281 #define CONFIG_TSEC2
 282 #define CONFIG_TSEC2_NAME       "TSEC1"
 283 #define CONFIG_PHY_M88E1111
 284 #define TSEC1_PHY_ADDR          0x08
 285 #define TSEC2_PHY_ADDR          0x10
 286 #define TSEC1_PHYIDX            0
 287 #define TSEC2_PHYIDX            0
 288 #define TSEC1_FLAGS             TSEC_GIGABIT
 289 #define TSEC2_FLAGS             TSEC_GIGABIT
 290
 291 /* Options are: TSEC[0-1] */
 292 #define CONFIG_ETHPRIME         "TSEC0"
 293
 294 #endif  /* CONFIG_TSEC_ENET */
 295
 296 /*
 297  * Environment
 298  */
 299 #ifndef CONFIG_SYS_RAMBOOT
 300         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0xc0000)
 301         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 302         #define CONFIG_ENV_SIZE         0x2000
 303
 304 /* Address and size of Redundant Environment Sector     */
 305 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 306 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 307
 308 #else
 309         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 310         #define CONFIG_ENV_SIZE         0x2000
 311 #endif
 312
 313 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 314 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 315
 316 /*
 317  * BOOTP options
 318  */
 319 #define CONFIG_BOOTP_BOOTFILESIZE
 320
 321 /*
 322  * Command line configuration.
 323  */
 324 #define CONFIG_SYS_RTC_BUS_NUM  0x01
 325 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
 326 #define CONFIG_RTC_RX8025
 327
 328 /* Pass Ethernet MAC to VxWorks */
 329 #define CONFIG_SYS_VXWORKS_MAC_PTR      0x000043f0
 330
 331 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 332
 333 /*
 334  * Miscellaneous configurable options
 335  */
 336 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 337
 338 /*
 339  * For booting Linux, the board info and command line data
 340  * have to be in the first 256 MB of memory, since this is
 341  * the maximum mapped by the Linux kernel during initialization.
 342  */
 343 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Init Memory map for Linux*/
 344
 345 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 346
 347 #define CONFIG_SYS_HRCW_LOW (\
 348         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 349         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 350         HRCWL_CSB_TO_CLKIN |\
 351         HRCWL_VCO_1X2 |\
 352         HRCWL_CORE_TO_CSB_2X1)
 353
 354 #if defined(PCI_64BIT)
 355 #define CONFIG_SYS_HRCW_HIGH (\
 356         HRCWH_PCI_HOST |\
 357         HRCWH_64_BIT_PCI |\
 358         HRCWH_PCI1_ARBITER_ENABLE |\
 359         HRCWH_PCI2_ARBITER_DISABLE |\
 360         HRCWH_CORE_ENABLE |\
 361         HRCWH_FROM_0X00000100 |\
 362         HRCWH_BOOTSEQ_DISABLE |\
 363         HRCWH_SW_WATCHDOG_DISABLE |\
 364         HRCWH_ROM_LOC_LOCAL_16BIT |\
 365         HRCWH_TSEC1M_IN_GMII |\
 366         HRCWH_TSEC2M_IN_GMII)
 367 #else
 368 #define CONFIG_SYS_HRCW_HIGH (\
 369         HRCWH_PCI_HOST |\
 370         HRCWH_32_BIT_PCI |\
 371         HRCWH_PCI1_ARBITER_ENABLE |\
 372         HRCWH_PCI2_ARBITER_ENABLE |\
 373         HRCWH_CORE_ENABLE |\
 374         HRCWH_FROM_0X00000100 |\
 375         HRCWH_BOOTSEQ_DISABLE |\
 376         HRCWH_SW_WATCHDOG_DISABLE |\
 377         HRCWH_ROM_LOC_LOCAL_16BIT |\
 378         HRCWH_TSEC1M_IN_GMII |\
 379         HRCWH_TSEC2M_IN_GMII)
 380 #endif
 381
 382 /* System IO Config */
 383 #define CONFIG_SYS_SICRH 0
 384 #define CONFIG_SYS_SICRL SICRL_LDP_A
 385
 386 #define CONFIG_SYS_HID0_INIT    0x000000000
 387 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 388                                  HID0_ENABLE_INSTRUCTION_CACHE)
 389
 390 #define CONFIG_SYS_HID2         HID2_HBE
 391
 392 #define CONFIG_SYS_GPIO1_PRELIM
 393 #define CONFIG_SYS_GPIO1_DIR    0x00100000
 394 #define CONFIG_SYS_GPIO1_DAT    0x00100000
 395
 396 #define CONFIG_SYS_GPIO2_PRELIM
 397 #define CONFIG_SYS_GPIO2_DIR    0x78900000
 398 #define CONFIG_SYS_GPIO2_DAT    0x70100000
 399
 400 #define CONFIG_HIGH_BATS                /* High BATs supported */
 401
 402 /* DDR @ 0x00000000 */
 403 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 404                                  BATL_MEMCOHERENCE)
 405 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
 406                                  BATU_VS | BATU_VP)
 407
 408 /* PCI @ 0x80000000 */
 409 #ifdef CONFIG_PCI
 410 #define CONFIG_PCI_INDIRECT_BRIDGE
 411 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
 412                                  BATL_MEMCOHERENCE)
 413 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
 414                                  BATU_VS | BATU_VP)
 415 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \
 416                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 417 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
 418                                  BATU_VS | BATU_VP)
 419 #else
 420 #define CONFIG_SYS_IBAT1L       (0)
 421 #define CONFIG_SYS_IBAT1U       (0)
 422 #define CONFIG_SYS_IBAT2L       (0)
 423 #define CONFIG_SYS_IBAT2U       (0)
 424 #endif
 425
 426 #ifdef CONFIG_MPC83XX_PCI2
 427 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \
 428                                  BATL_MEMCOHERENCE)
 429 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
 430                                  BATU_VS | BATU_VP)
 431 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \
 432                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 433 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
 434                                  BATU_VS | BATU_VP)
 435 #else
 436 #define CONFIG_SYS_IBAT3L       (0)
 437 #define CONFIG_SYS_IBAT3U       (0)
 438 #define CONFIG_SYS_IBAT4L       (0)
 439 #define CONFIG_SYS_IBAT4U       (0)
 440 #endif
 441
 442 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
 443 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 444                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 445 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR | BATU_BL_256M | \
 446                                  BATU_VS | BATU_VP)
 447
 448 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE)
 449 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 450
 451 #if (CONFIG_SYS_DDR_SIZE == 512)
 452 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
 453                                  BATL_PP_RW | BATL_MEMCOHERENCE)
 454 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
 455                                  BATU_BL_256M | BATU_VS | BATU_VP)
 456 #else
 457 #define CONFIG_SYS_IBAT7L       (0)
 458 #define CONFIG_SYS_IBAT7U       (0)
 459 #endif
 460
 461 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 462 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 463 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 464 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 465 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 466 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 467 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 468 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 469 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 470 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 471 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 472 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 473 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 474 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 475 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 476 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 477
 478 #if defined(CONFIG_CMD_KGDB)
 479 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 480 #endif
 481
 482 /*
 483  * Environment Configuration
 484  */
 485 #define CONFIG_ENV_OVERWRITE
 486
 487 #if defined(CONFIG_TSEC_ENET)
 488 #define CONFIG_HAS_ETH0
 489 #define CONFIG_HAS_ETH1
 490 #endif
 491
 492 #define CONFIG_HOSTNAME         "VME8349"
 493 #define CONFIG_ROOTPATH         "/tftpboot/rootfs"
 494 #define CONFIG_BOOTFILE         "uImage"
 495
 496 #define CONFIG_LOADADDR         800000  /* def location for tftp and bootm */
 497
 498 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 499         "netdev=eth0\0"                                                 \
 500         "hostname=vme8349\0"                                            \
 501         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 502                 "nfsroot=${serverip}:${rootpath}\0"                     \
 503         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 504         "addip=setenv bootargs ${bootargs} "                            \
 505                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 506                 ":${hostname}:${netdev}:off panic=1\0"                  \
 507         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 508         "flash_nfs=run nfsargs addip addtty;"                           \
 509                 "bootm ${kernel_addr}\0"                                \
 510         "flash_self=run ramargs addip addtty;"                          \
 511                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 512         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 513                 "bootm\0"                                               \
 514         "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0"              \
 515         "update=protect off fff00000 fff3ffff; "                        \
 516                 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
 517         "upd=run load update\0"                                         \
 518         "fdtaddr=780000\0"                                              \
 519         "fdtfile=vme8349.dtb\0"                                         \
 520         ""
 521
 522 #define CONFIG_NFSBOOTCOMMAND                                           \
 523         "setenv bootargs root=/dev/nfs rw "                             \
 524                 "nfsroot=$serverip:$rootpath "                          \
 525                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 526                                                         "$netdev:off "  \
 527                 "console=$consoledev,$baudrate $othbootargs;"           \
 528         "tftp $loadaddr $bootfile;"                                     \
 529         "tftp $fdtaddr $fdtfile;"                                       \
 530         "bootm $loadaddr - $fdtaddr"
 531
 532 #define CONFIG_RAMBOOTCOMMAND                                           \
 533         "setenv bootargs root=/dev/ram rw "                             \
 534                 "console=$consoledev,$baudrate $othbootargs;"           \
 535         "tftp $ramdiskaddr $ramdiskfile;"                               \
 536         "tftp $loadaddr $bootfile;"                                     \
 537         "tftp $fdtaddr $fdtfile;"                                       \
 538         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 539
 540 #define CONFIG_BOOTCOMMAND      "run flash_self"
 541
 542 #ifndef __ASSEMBLY__
 543 int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
 544                      unsigned char *buffer, int len);
 545 #endif
 546
 547 #endif  /* __CONFIG_H */