2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
4 * (C) Copyright 2009 Freescale Semiconductor, Inc.
6 * Configuration settings for the MX51-3Stack Freescale board.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #define CONFIG_MX51 /* in a mx51 */
29 #define CONFIG_SYS_TEXT_BASE 0x97800000
31 #include <asm/arch/imx-regs.h>
33 #define CONFIG_SYS_MX5_HCLK 24000000
34 #define CONFIG_SYS_MX5_CLK32 32768
35 #define CONFIG_DISPLAY_CPUINFO
36 #define CONFIG_DISPLAY_BOARDINFO
38 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
39 #define CONFIG_REVISION_TAG
40 #define CONFIG_SETUP_MEMORY_TAGS
41 #define CONFIG_INITRD_TAG
42 #define CONFIG_BOARD_LATE_INIT
44 #ifndef MACH_TYPE_TTC_VISION2
45 #define MACH_TYPE_TTC_VISION2 2775
47 #define CONFIG_MACH_TYPE MACH_TYPE_TTC_VISION2
50 * Size of malloc() pool
52 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
57 #define CONFIG_MXC_UART
58 #define CONFIG_SYS_MX51_UART3
59 #define CONFIG_MXC_GPIO
60 #define CONFIG_MXC_SPI
61 #define CONFIG_HW_WATCHDOG
69 #define CONFIG_SPI_FLASH
70 #define CONFIG_SPI_FLASH_STMICRO
73 * Use gpio 4 pin 25 as chip select for SPI flash
74 * This corresponds to gpio 121
76 #define CONFIG_SPI_FLASH_CS (1 | (121 << 8))
77 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
78 #define CONFIG_SF_DEFAULT_SPEED 25000000
80 #define CONFIG_ENV_SPI_CS (1 | (121 << 8))
81 #define CONFIG_ENV_SPI_BUS 0
82 #define CONFIG_ENV_SPI_MAX_HZ 25000000
83 #define CONFIG_ENV_SPI_MODE SPI_MODE_0
85 #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
86 #define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024)
87 #define CONFIG_ENV_SIZE (4 * 1024)
89 #define CONFIG_FSL_ENV_IN_SF
90 #define CONFIG_ENV_IS_IN_SPI_FLASH
94 #define CONFIG_PMIC_SPI
95 #define CONFIG_PMIC_FSL
96 #define CONFIG_FSL_PMIC_BUS 0
97 #define CONFIG_FSL_PMIC_CS 0
98 #define CONFIG_FSL_PMIC_CLK 2500000
99 #define CONFIG_FSL_PMIC_MODE SPI_MODE_0
100 #define CONFIG_FSL_PMIC_BITLEN 32
101 #define CONFIG_RTC_MC13XXX
106 #define CONFIG_FSL_ESDHC
107 #ifdef CONFIG_FSL_ESDHC
108 #define CONFIG_SYS_FSL_ESDHC_ADDR (0x70004000)
109 #define CONFIG_SYS_FSL_ESDHC_NUM 1
113 #define CONFIG_CMD_MMC
114 #define CONFIG_GENERIC_MMC
115 #define CONFIG_CMD_FAT
116 #define CONFIG_DOS_PARTITION
119 #define CONFIG_CMD_DATE
124 #define CONFIG_HAS_ETH1
126 #define CONFIG_DISCOVER_PHY
128 #define CONFIG_FEC_MXC
129 #define IMX_FEC_BASE FEC_BASE_ADDR
130 #define CONFIG_FEC_MXC_PHYADDR 0x1F
132 #define CONFIG_CMD_PING
133 #define CONFIG_CMD_MII
134 #define CONFIG_CMD_NET
136 /* allow to overwrite serial and ethaddr */
137 #define CONFIG_ENV_OVERWRITE
138 #define CONFIG_CONS_INDEX 3
139 #define CONFIG_BAUDRATE 115200
140 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
142 /***********************************************************
144 ***********************************************************/
146 #include <config_cmd_default.h>
148 #define CONFIG_CMD_SPI
149 #undef CONFIG_CMD_IMLS
151 #define CONFIG_BOOTDELAY 3
153 #define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
155 #define CONFIG_EXTRA_ENV_SETTINGS \
157 "loadaddr=0x90800000\0"
160 * Miscellaneous configurable options
162 #define CONFIG_SYS_LONGHELP
163 #define CONFIG_SYS_PROMPT "Vision II U-boot > "
164 #define CONFIG_AUTO_COMPLETE
165 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
167 /* Print Buffer Size */
168 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
169 sizeof(CONFIG_SYS_PROMPT) + 16)
170 #define CONFIG_SYS_MAXARGS 64 /* max number of command args */
171 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
173 #define CONFIG_SYS_MEMTEST_START 0x90000000
174 #define CONFIG_SYS_MEMTEST_END 0x10000
176 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
178 #define CONFIG_SYS_HZ 1000
179 #define CONFIG_CMDLINE_EDITING
180 #define CONFIG_SYS_HUSH_PARSER
181 #define CONFIG_SYS_PROMPT_HUSH_PS2 "Vision II U-boot > "
186 #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
189 * Physical Memory Map
191 #define CONFIG_NR_DRAM_BANKS 2
192 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
193 #define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
194 #define PHYS_SDRAM_2 CSD1_BASE_ADDR
195 #define PHYS_SDRAM_2_SIZE (256 * 1024 * 1024)
196 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
197 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
198 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
200 #define CONFIG_SYS_INIT_SP_OFFSET \
201 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
202 #define CONFIG_SYS_INIT_SP_ADDR \
203 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
205 #define CONFIG_BOARD_EARLY_INIT_F
207 /* 166 MHz DDR RAM */
208 #define CONFIG_SYS_DDR_CLKSEL 0
209 #define CONFIG_SYS_CLKTL_CBCDR 0x19239100
211 #define CONFIG_SYS_NO_FLASH
214 * Framebuffer and LCD
216 #define CONFIG_PREBOOT
218 #define CONFIG_VIDEO_MX5
219 #define CONFIG_CFB_CONSOLE
220 #define CONFIG_VGA_AS_SINGLE_DEVICE
221 #define CONFIG_VIDEO_BMP_RLE8
222 #define CONFIG_SPLASH_SCREEN
223 #define CONFIG_CMD_BMP
224 #define CONFIG_BMP_16BPP
226 #endif /* __CONFIG_H */