ARM: configs: Add da850evm_nand to boot from NAND
[oweals/u-boot.git] / include / configs / vexpress_common.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2011 ARM Limited
4  * (C) Copyright 2010 Linaro
5  * Matt Waddel, <matt.waddel@linaro.org>
6  *
7  * Configuration for Versatile Express. Parts were derived from other ARM
8  *   configurations.
9  */
10
11 #ifndef __VEXPRESS_COMMON_H
12 #define __VEXPRESS_COMMON_H
13
14 /*
15  * Definitions copied from linux kernel:
16  * arch/arm/mach-vexpress/include/mach/motherboard.h
17  */
18 #ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
19 /* CS register bases for the original memory map. */
20 #define V2M_PA_CS0              0x40000000
21 #define V2M_PA_CS1              0x44000000
22 #define V2M_PA_CS2              0x48000000
23 #define V2M_PA_CS3              0x4c000000
24 #define V2M_PA_CS7              0x10000000
25
26 #define V2M_PERIPH_OFFSET(x)    (x << 12)
27 #define V2M_SYSREGS             (V2M_PA_CS7 + V2M_PERIPH_OFFSET(0))
28 #define V2M_SYSCTL              (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
29 #define V2M_SERIAL_BUS_PCI      (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
30
31 #define V2M_BASE                0x60000000
32 #elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
33 /* CS register bases for the extended memory map. */
34 #define V2M_PA_CS0              0x08000000
35 #define V2M_PA_CS1              0x0c000000
36 #define V2M_PA_CS2              0x14000000
37 #define V2M_PA_CS3              0x18000000
38 #define V2M_PA_CS7              0x1c000000
39
40 #define V2M_PERIPH_OFFSET(x)    (x << 16)
41 #define V2M_SYSREGS             (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
42 #define V2M_SYSCTL              (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
43 #define V2M_SERIAL_BUS_PCI      (V2M_PA_CS7 + V2M_PERIPH_OFFSET(3))
44
45 #define V2M_BASE                0x80000000
46 #endif
47
48 /*
49  * Physical addresses, offset from V2M_PA_CS0-3
50  */
51 #define V2M_NOR0                (V2M_PA_CS0)
52 #define V2M_NOR1                (V2M_PA_CS1)
53 #define V2M_SRAM                (V2M_PA_CS2)
54 #define V2M_VIDEO_SRAM          (V2M_PA_CS3 + 0x00000000)
55 #define V2M_ISP1761             (V2M_PA_CS3 + 0x03000000)
56
57 /* Common peripherals relative to CS7. */
58 #define V2M_AACI                (V2M_PA_CS7 + V2M_PERIPH_OFFSET(4))
59 #define V2M_MMCI                (V2M_PA_CS7 + V2M_PERIPH_OFFSET(5))
60 #define V2M_KMI0                (V2M_PA_CS7 + V2M_PERIPH_OFFSET(6))
61 #define V2M_KMI1                (V2M_PA_CS7 + V2M_PERIPH_OFFSET(7))
62
63 #define V2M_UART0               (V2M_PA_CS7 + V2M_PERIPH_OFFSET(9))
64 #define V2M_UART1               (V2M_PA_CS7 + V2M_PERIPH_OFFSET(10))
65 #define V2M_UART2               (V2M_PA_CS7 + V2M_PERIPH_OFFSET(11))
66 #define V2M_UART3               (V2M_PA_CS7 + V2M_PERIPH_OFFSET(12))
67
68 #define V2M_WDT                 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(15))
69
70 #define V2M_TIMER01             (V2M_PA_CS7 + V2M_PERIPH_OFFSET(17))
71 #define V2M_TIMER23             (V2M_PA_CS7 + V2M_PERIPH_OFFSET(18))
72
73 #define V2M_SERIAL_BUS_DVI      (V2M_PA_CS7 + V2M_PERIPH_OFFSET(22))
74 #define V2M_RTC                 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(23))
75
76 #define V2M_CF                  (V2M_PA_CS7 + V2M_PERIPH_OFFSET(26))
77
78 #define V2M_CLCD                (V2M_PA_CS7 + V2M_PERIPH_OFFSET(31))
79 #define V2M_SIZE_CS7            V2M_PERIPH_OFFSET(32)
80
81 /* System register offsets. */
82 #define V2M_SYS_CFGDATA         (V2M_SYSREGS + 0x0a0)
83 #define V2M_SYS_CFGCTRL         (V2M_SYSREGS + 0x0a4)
84 #define V2M_SYS_CFGSTAT         (V2M_SYSREGS + 0x0a8)
85
86 /*
87  * Configuration
88  */
89 #define SYS_CFG_START           (1 << 31)
90 #define SYS_CFG_WRITE           (1 << 30)
91 #define SYS_CFG_OSC             (1 << 20)
92 #define SYS_CFG_VOLT            (2 << 20)
93 #define SYS_CFG_AMP             (3 << 20)
94 #define SYS_CFG_TEMP            (4 << 20)
95 #define SYS_CFG_RESET           (5 << 20)
96 #define SYS_CFG_SCC             (6 << 20)
97 #define SYS_CFG_MUXFPGA         (7 << 20)
98 #define SYS_CFG_SHUTDOWN        (8 << 20)
99 #define SYS_CFG_REBOOT          (9 << 20)
100 #define SYS_CFG_DVIMODE         (11 << 20)
101 #define SYS_CFG_POWER           (12 << 20)
102 #define SYS_CFG_SITE_MB         (0 << 16)
103 #define SYS_CFG_SITE_DB1        (1 << 16)
104 #define SYS_CFG_SITE_DB2        (2 << 16)
105 #define SYS_CFG_STACK(n)        ((n) << 12)
106
107 #define SYS_CFG_ERR             (1 << 1)
108 #define SYS_CFG_COMPLETE        (1 << 0)
109
110 /* Board info register */
111 #define SYS_ID                          V2M_SYSREGS
112 #define CONFIG_REVISION_TAG             1
113
114 #define CONFIG_SYS_MEMTEST_START        V2M_BASE
115 #define CONFIG_SYS_MEMTEST_END          0x20000000
116
117 #define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
118 #define CONFIG_SETUP_MEMORY_TAGS        1
119 #define CONFIG_SYS_L2CACHE_OFF          1
120 #define CONFIG_INITRD_TAG               1
121
122 /* Size of malloc() pool */
123 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 128 * 1024)
124
125 #define SCTL_BASE                       V2M_SYSCTL
126 #define VEXPRESS_FLASHPROG_FLVPPEN      (1 << 0)
127
128 #define CONFIG_SYS_TIMER_RATE           1000000
129 #define CONFIG_SYS_TIMER_COUNTER        (V2M_TIMER01 + 0x4)
130 #define CONFIG_SYS_TIMER_COUNTS_DOWN
131
132 /* PL011 Serial Configuration */
133 #define CONFIG_PL011_CLOCK              24000000
134 #define CONFIG_PL01x_PORTS              {(void *)CONFIG_SYS_SERIAL0, \
135                                          (void *)CONFIG_SYS_SERIAL1}
136
137 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
138 #define CONFIG_SYS_SERIAL0              V2M_UART0
139 #define CONFIG_SYS_SERIAL1              V2M_UART1
140
141 #define CONFIG_ARM_PL180_MMCI
142 #define CONFIG_ARM_PL180_MMCI_BASE      V2M_MMCI
143 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    127
144 #define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000
145
146 /* BOOTP options */
147 #define CONFIG_BOOTP_BOOTFILESIZE
148
149 /* Miscellaneous configurable options */
150 #define CONFIG_SYS_LOAD_ADDR            (V2M_BASE + 0x8000)
151 #define LINUX_BOOT_PARAM_ADDR           (V2M_BASE + 0x2000)
152
153 /* Physical Memory Map */
154 #define PHYS_SDRAM_1                    (V2M_BASE)      /* SDRAM Bank #1 */
155 #define PHYS_SDRAM_2                    (((unsigned int)V2M_BASE) + \
156                                         ((unsigned int)0x20000000))
157 #define PHYS_SDRAM_1_SIZE               0x20000000      /* 512 MB */
158 #define PHYS_SDRAM_2_SIZE               0x20000000      /* 512 MB */
159
160 /* additions for new relocation code */
161 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
162 #define CONFIG_SYS_INIT_RAM_SIZE                0x1000
163 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_SDRAM_BASE + \
164                                          CONFIG_SYS_INIT_RAM_SIZE - \
165                                          GENERATED_GBL_DATA_SIZE)
166 #define CONFIG_SYS_INIT_SP_ADDR         CONFIG_SYS_GBL_DATA_OFFSET
167
168 /* Basic environment settings */
169 #define BOOT_TARGET_DEVICES(func) \
170         func(MMC, mmc, 1) \
171         func(MMC, mmc, 0) \
172         func(PXE, pxe, na) \
173         func(DHCP, dhcp, na)
174 #include <config_distro_bootcmd.h>
175
176 #ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
177 #define CONFIG_PLATFORM_ENV_SETTINGS \
178                 "loadaddr=0x80008000\0" \
179                 "ramdisk_addr_r=0x61000000\0" \
180                 "kernel_addr=0x44100000\0" \
181                 "ramdisk_addr=0x44800000\0" \
182                 "maxramdisk=0x1800000\0" \
183                 "pxefile_addr_r=0x88000000\0" \
184                 "scriptaddr=0x88000000\0" \
185                 "kernel_addr_r=0x80008000\0"
186 #elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
187 #define CONFIG_PLATFORM_ENV_SETTINGS \
188                 "loadaddr=0xa0008000\0" \
189                 "ramdisk_addr_r=0x81000000\0" \
190                 "kernel_addr=0x0c100000\0" \
191                 "ramdisk_addr=0x0c800000\0" \
192                 "maxramdisk=0x1800000\0" \
193                 "pxefile_addr_r=0xa8000000\0" \
194                 "scriptaddr=0xa8000000\0" \
195                 "kernel_addr_r=0xa0008000\0"
196 #endif
197 #define CONFIG_EXTRA_ENV_SETTINGS \
198                 CONFIG_PLATFORM_ENV_SETTINGS \
199                 BOOTENV \
200                 "console=ttyAMA0,38400n8\0" \
201                 "dram=1024M\0" \
202                 "root=/dev/sda1 rw\0" \
203                 "mtd=armflash:1M@0x800000(uboot),7M@0x1000000(kernel)," \
204                         "24M@0x2000000(initrd)\0" \
205                 "flashargs=setenv bootargs root=${root} console=${console} " \
206                         "mem=${dram} mtdparts=${mtd} mmci.fmax=190000 " \
207                         "devtmpfs.mount=0  vmalloc=256M\0" \
208                 "bootflash=run flashargs; " \
209                         "cp ${ramdisk_addr} ${ramdisk_addr_r} ${maxramdisk}; " \
210                         "bootm ${kernel_addr} ${ramdisk_addr_r}\0"
211
212 /* FLASH and environment organization */
213 #define PHYS_FLASH_SIZE                 0x04000000      /* 64MB */
214 #define CONFIG_SYS_FLASH_CFI            1
215 #define CONFIG_FLASH_CFI_DRIVER         1
216 #define CONFIG_SYS_FLASH_SIZE           0x04000000
217 #define CONFIG_SYS_MAX_FLASH_BANKS      2
218 #define CONFIG_SYS_FLASH_BASE0          V2M_NOR0
219 #define CONFIG_SYS_FLASH_BASE1          V2M_NOR1
220 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE0
221
222 /* Timeout values in ticks */
223 #define CONFIG_SYS_FLASH_ERASE_TOUT     (2 * CONFIG_SYS_HZ) /* Erase Timeout */
224 #define CONFIG_SYS_FLASH_WRITE_TOUT     (2 * CONFIG_SYS_HZ) /* Write Timeout */
225
226 /* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
227 #define CONFIG_SYS_MAX_FLASH_SECT       259             /* Max sectors */
228 #define FLASH_MAX_SECTOR_SIZE           0x00040000      /* 256 KB sectors */
229
230 /* Room required on the stack for the environment data */
231 #define CONFIG_ENV_SIZE                 FLASH_MAX_SECTOR_SIZE
232
233 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
234
235 /*
236  * Amount of flash used for environment:
237  * We don't know which end has the small erase blocks so we use the penultimate
238  * sector location for the environment
239  */
240 #define CONFIG_ENV_SECT_SIZE            FLASH_MAX_SECTOR_SIZE
241 #define CONFIG_ENV_OVERWRITE            1
242
243 /* Store environment at top of flash */
244 #define CONFIG_ENV_OFFSET               (PHYS_FLASH_SIZE - \
245                                         (2 * CONFIG_ENV_SECT_SIZE))
246 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE1 + \
247                                          CONFIG_ENV_OFFSET)
248 #define CONFIG_SYS_FLASH_PROTECTION     /* The devices have real protection */
249 #define CONFIG_SYS_FLASH_EMPTY_INFO     /* flinfo indicates empty blocks */
250 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE0, \
251                                           CONFIG_SYS_FLASH_BASE1 }
252
253 /* Monitor Command Prompt */
254 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
255
256 #endif /* VEXPRESS_COMMON_H */