1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * USB armory MkI board configuration settings
4 * http://inversepath.com/usbarmory
6 * Copyright (C) 2015, Inverse Path
7 * Andrej Rosano <andrej@inversepath.com>
13 #define CONFIG_SYS_FSL_CLK
15 #include <asm/arch/imx-regs.h>
17 /* U-Boot environment */
18 #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
19 #define CONFIG_ENV_SIZE (8 * 1024)
20 #define CONFIG_SYS_MMC_ENV_DEV 0
22 /* U-Boot general configurations */
23 #define CONFIG_SYS_CBSIZE 512
26 #define CONFIG_MXC_UART
27 #define CONFIG_MXC_UART_BASE UART1_BASE
30 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
31 #define CONFIG_SYS_FSL_ESDHC_NUM 1
34 #define CONFIG_MXC_USB_PORT 1
35 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
36 #define CONFIG_MXC_USB_FLAGS 0
39 #define CONFIG_SYS_I2C
40 #define CONFIG_SYS_I2C_MXC
41 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
42 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
45 #define CONFIG_FSL_IIM
47 /* U-Boot memory offsets */
48 #define CONFIG_LOADADDR 0x72000000
49 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
52 #define CONFIG_HOSTNAME "usbarmory"
53 #define CONFIG_BOOTCOMMAND \
54 "run distro_bootcmd; " \
55 "setenv bootargs console=${console} ${bootargs_default}; " \
56 "ext2load mmc 0:1 ${kernel_addr_r} /boot/zImage; " \
57 "ext2load mmc 0:1 ${fdt_addr_r} /boot/${fdtfile}; " \
58 "bootz ${kernel_addr_r} - ${fdt_addr_r}"
60 #define BOOT_TARGET_DEVICES(func) func(MMC, mmc, 0)
62 #include <config_distro_bootcmd.h>
64 #define MEM_LAYOUT_ENV_SETTINGS \
65 "kernel_addr_r=0x70800000\0" \
66 "fdt_addr_r=0x71000000\0" \
67 "scriptaddr=0x70800000\0" \
68 "pxefile_addr_r=0x70800000\0" \
69 "ramdisk_addr_r=0x73000000\0"
71 #define CONFIG_EXTRA_ENV_SETTINGS \
72 MEM_LAYOUT_ENV_SETTINGS \
73 "bootargs_default=root=/dev/mmcblk0p1 rootwait rw\0" \
74 "fdtfile=imx53-usbarmory.dtb\0" \
75 "console=ttymxc0,115200\0" \
78 #ifndef CONFIG_CMDLINE
79 #define USBARMORY_FIT_PATH "/boot/usbarmory.itb"
80 #define USBARMORY_FIT_ADDR "0x70800000"
83 /* Physical Memory Map */
84 #define PHYS_SDRAM CSD0_BASE_ADDR
85 #define PHYS_SDRAM_SIZE (gd->ram_size)
87 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
88 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
89 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
91 #define CONFIG_SYS_INIT_SP_OFFSET \
92 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
93 #define CONFIG_SYS_INIT_SP_ADDR \
94 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
96 #define CONFIG_SYS_MEMTEST_START 0x70000000
97 #define CONFIG_SYS_MEMTEST_END 0x90000000
99 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
101 #endif /* __CONFIG_H */