2 * (C) Copyright 2003-2006
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
32 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
33 #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
34 #define CONFIG_UC101 1 /* UC101 board */
36 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
38 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
39 #define BOOTFLAG_WARM 0x02 /* Software reboot */
41 #define CONFIG_BOARD_EARLY_INIT_R
44 * Serial console configuration
46 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
47 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
48 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
51 #define CONFIG_DOS_PARTITION
55 * Command line configuration.
57 #include <config_cmd_default.h>
59 #define CONFIG_CMD_DATE
60 #define CONFIG_CMD_DISPLAY
61 #define CONFIG_CMD_DHCP
62 #define CONFIG_CMD_PING
63 #define CONFIG_CMD_EEPROM
64 #define CONFIG_CMD_I2C
65 #define CONFIG_CMD_DTT
66 #define CONFIG_CMD_IDE
67 #define CONFIG_CMD_FAT
68 #define CONFIG_CMD_NFS
69 #define CONFIG_CMD_MII
70 #define CONFIG_CMD_SNTP
73 #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
75 #if (TEXT_BASE == 0xFFF00000) /* Boot low */
76 # define CFG_LOWBOOT 1
82 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
84 #define CONFIG_PREBOOT "echo;" \
85 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
88 #undef CONFIG_BOOTARGS
90 #define CONFIG_EXTRA_ENV_SETTINGS \
92 "nfsargs=setenv bootargs root=/dev/nfs rw " \
93 "nfsroot=${serverip}:${rootpath}\0" \
94 "ramargs=setenv bootargs root=/dev/ram rw\0" \
95 "addwdt=setenv bootargs ${bootargs} wdt=off" \
96 "addip=setenv bootargs ${bootargs} " \
97 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
98 ":${hostname}:${netdev}:off panic=1\0" \
99 "flash_nfs=run nfsargs addip;" \
100 "bootm ${kernel_addr}\0" \
101 "net_nfs=tftp 300000 ${bootfile};run nfsargs addip addwdt;bootm\0" \
102 "rootpath=/opt/eldk/ppc_82xx\0" \
105 #define CONFIG_BOOTCOMMAND "run net_nfs"
107 #define CONFIG_MISC_INIT_R 1
110 * IPB Bus clocking configuration.
112 #define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
117 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
118 #define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
120 #define CFG_I2C_SPEED 100000 /* 100 kHz */
121 #define CFG_I2C_SLAVE 0x7F
124 * EEPROM configuration
126 #define CFG_I2C_EEPROM_ADDR 0x58
127 #define CFG_I2C_EEPROM_ADDR_LEN 1
128 #define CFG_EEPROM_PAGE_WRITE_BITS 4
129 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
131 #define CFG_EEPROM_PAGE_WRITE_ENABLE
136 #define CONFIG_RTC_PCF8563
137 #define CFG_I2C_RTC_ADDR 0x51
139 /* I2C SYSMON (LM75) */
140 #define CONFIG_DTT_LM81 1 /* ON Semi's LM75 */
141 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
142 #define CFG_DTT_MAX_TEMP 70
143 #define CFG_DTT_LOW_TEMP -30
144 #define CFG_DTT_HYSTERESIS 3
147 * Flash configuration
149 #define CFG_FLASH_BASE 0xFF800000
151 #define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */
152 #define CFG_MAX_FLASH_SECT 140 /* max num of sects on one chip */
154 #define CFG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */
155 #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
157 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
158 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
160 #define CFG_FLASH_CFI_DRIVER
161 #define CFG_FLASH_CFI
162 #define CFG_FLASH_EMPTY_INFO
163 #define CFG_FLASH_CFI_AMD_RESET
166 * Environment settings
168 #define CFG_ENV_IS_IN_FLASH 1
169 #define CFG_ENV_SIZE 0x4000
170 #define CFG_ENV_SECT_SIZE 0x10000
171 #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
172 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
177 #define CFG_MBAR 0xF0000000
178 #define CFG_DEFAULT_MBAR 0x80000000
180 #define CFG_SDRAM_BASE 0x00000000
181 #define CFG_SRAM_BASE 0x80100000 /* CS 1 */
182 #define CFG_DISPLAY_BASE 0x80600000 /* CS 3 */
183 #define CFG_IB_MASTER 0xc0510000 /* CS 6 */
184 #define CFG_IB_EPLD 0xc0500000 /* CS 7 */
186 /* Settings for XLB = 132 MHz */
188 #define SDRAM_MODE 0x018D0000
189 #define SDRAM_EMODE 0x40090000
190 #define SDRAM_CONTROL 0x714f0f00
191 #define SDRAM_CONFIG1 0x73722930
192 #define SDRAM_CONFIG2 0x47770000
193 #define SDRAM_TAPDELAY 0x10000000
196 #define SRAM_BASE CFG_SRAM_BASE /* SRAM base address */
197 #define SRAM_LEN 0x1fffff
198 #define SRAM_END (SRAM_BASE + SRAM_LEN)
200 /* Use ON-Chip SRAM until RAM will be available */
201 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
203 /* preserve space for the post_word at end of on-chip SRAM */
204 #define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
206 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
210 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
211 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
212 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
214 #define CFG_MONITOR_BASE TEXT_BASE
215 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
216 # define CFG_RAMBOOT 1
219 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
220 #define CFG_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */
221 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
224 * Ethernet configuration
226 #define CONFIG_MPC5xxx_FEC 1
227 #define CONFIG_PHY_ADDR 0x00
233 #define CFG_GPS_PORT_CONFIG 0x4d558044
235 /*use Hardware WDT */
236 #define CONFIG_HW_WATCHDOG
239 * Miscellaneous configurable options
241 #define CFG_LONGHELP /* undef to save memory */
242 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
243 #if defined(CONFIG_CMD_KGDB)
244 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
246 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
248 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
249 #define CFG_MAXARGS 16 /* max number of command args */
250 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
252 /* Enable an alternate, more extensive memory test */
253 #define CFG_ALT_MEMTEST
255 #define CFG_MEMTEST_START 0x00300000 /* memtest works on */
256 #define CFG_MEMTEST_END 0x00f00000 /* 3 ... 15 MB in DRAM */
258 #define CFG_LOAD_ADDR 0x300000 /* default load address */
260 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
262 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
263 #if defined(CONFIG_CMD_KGDB)
264 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
268 * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
269 * which is normally part of the default commands (CFV_CMD_DFL)
274 * Various low-level settings
276 #if defined(CONFIG_MPC5200)
277 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
278 #define CFG_HID0_FINAL HID0_ICE
280 #define CFG_HID0_INIT 0
281 #define CFG_HID0_FINAL 0
284 #define CFG_BOOTCS_START CFG_FLASH_BASE
285 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
286 #define CFG_BOOTCS_CFG 0x00045D00
287 #define CFG_CS0_START CFG_FLASH_BASE
288 #define CFG_CS0_SIZE CFG_FLASH_SIZE
290 /* 8Mbit SRAM @0x80100000 */
291 #define CFG_CS1_START CFG_SRAM_BASE
292 #define CFG_CS1_SIZE 0x00100000
293 #define CFG_CS1_CFG 0x21D00
295 /* Display H1, Status Inputs, EPLD @0x80600000 8 Bit */
296 #define CFG_CS3_START CFG_DISPLAY_BASE
297 #define CFG_CS3_SIZE 0x00000100
298 #define CFG_CS3_CFG 0x00081802
300 /* Interbus Master 16 Bit */
301 #define CFG_CS6_START CFG_IB_MASTER
302 #define CFG_CS6_SIZE 0x00010000
303 #define CFG_CS6_CFG 0x00FF3500
305 /* Interbus EPLD 8 Bit */
306 #define CFG_CS7_START CFG_IB_EPLD
307 #define CFG_CS7_SIZE 0x00010000
308 #define CFG_CS7_CFG 0x00081800
310 #define CFG_CS_BURST 0x00000000
311 #define CFG_CS_DEADCYCLE 0x33333333
313 /*-----------------------------------------------------------------------
314 * IDE/ATA stuff Supports IDE harddisk
315 *-----------------------------------------------------------------------
318 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
320 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
321 #undef CONFIG_IDE_LED /* LED for ide not supported */
323 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
324 #define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
326 #define CONFIG_IDE_PREINIT 1
327 /* #define CONFIG_IDE_RESET 1 beispile siehe tqm5200.c */
329 #define CFG_ATA_IDE0_OFFSET 0x0000
331 #define CFG_ATA_BASE_ADDR MPC5XXX_ATA
333 /* Offset for data I/O */
334 #define CFG_ATA_DATA_OFFSET (0x0060)
336 /* Offset for normal register accesses */
337 #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
339 /* Offset for alternate registers */
340 #define CFG_ATA_ALT_OFFSET (0x005C)
342 /* Interval between registers */
343 #define CFG_ATA_STRIDE 4
345 #define CONFIG_ATAPI 1
347 /*---------------------------------------------------------------------*/
348 /* Display addresses */
349 /*---------------------------------------------------------------------*/
350 #define CFG_DISP_CHR_RAM (CFG_DISPLAY_BASE + 0x38)
351 #define CFG_DISP_CWORD (CFG_DISPLAY_BASE + 0x30)
353 #endif /* __CONFIG_H */