sunxi: Add support for using MII phy-s with the GMAC nic
[oweals/u-boot.git] / include / configs / u8500_href.h
1 /*
2  * Copyright (C) ST-Ericsson SA 2009
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __CONFIG_H
8 #define __CONFIG_H
9
10 /*
11  * High Level Configuration Options
12  * (easy to change)
13  */
14 #define CONFIG_U8500
15
16 #define CONFIG_SYS_MEMTEST_START        0x00000000
17 #define CONFIG_SYS_MEMTEST_END  0x1FFFFFFF
18
19 #define CONFIG_BOARD_EARLY_INIT_F
20 #define CONFIG_BOARD_LATE_INIT
21
22 /*
23  * Size of malloc() pool
24  */
25 #ifdef CONFIG_BOOT_SRAM
26 #define CONFIG_ENV_SIZE         (32*1024)
27 #define CONFIG_SYS_MALLOC_LEN   (CONFIG_ENV_SIZE + 64*1024)
28 #else
29 #define CONFIG_ENV_SIZE         (128*1024)
30 #define CONFIG_SYS_MALLOC_LEN   (CONFIG_ENV_SIZE + 256*1024)
31 #endif
32
33 /*
34  * PL011 Configuration
35  */
36 #define CONFIG_PL011_SERIAL
37 #define CONFIG_PL011_SERIAL_RLCR
38 #define CONFIG_PL011_SERIAL_FLUSH_ON_INIT
39
40 /*
41  * U8500 UART registers base for 3 serial devices
42  */
43 #define CFG_UART0_BASE          0x80120000
44 #define CFG_UART1_BASE          0x80121000
45 #define CFG_UART2_BASE          0x80007000
46 #define CFG_SERIAL0             CFG_UART0_BASE
47 #define CFG_SERIAL1             CFG_UART1_BASE
48 #define CFG_SERIAL2             CFG_UART2_BASE
49 #define CONFIG_PL011_CLOCK      38400000
50 #define CONFIG_PL01x_PORTS      { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1, \
51                                   (void *)CFG_SERIAL2 }
52 #define CONFIG_CONS_INDEX       2
53 #define CONFIG_BAUDRATE         115200
54
55 /*
56  * Devices and file systems
57  */
58 #define CONFIG_MMC
59 #define CONFIG_GENERIC_MMC
60 #define CONFIG_DOS_PARTITION
61
62 /*
63  * Commands
64  */
65 #define CONFIG_CMD_MEMORY
66 #define CONFIG_CMD_BOOTD
67 #define CONFIG_CMD_BDI
68 #define CONFIG_CMD_IMI
69 #define CONFIG_CMD_MISC
70 #define CONFIG_CMD_RUN
71 #define CONFIG_CMD_ECHO
72 #define CONFIG_CMD_CONSOLE
73 #define CONFIG_CMD_LOADS
74 #define CONFIG_CMD_LOADB
75 #define CONFIG_CMD_MMC
76 #define CONFIG_CMD_FAT
77 #define CONFIG_CMD_EXT2
78 #define CONFIG_CMD_SOURCE
79 #define CONFIG_CMD_I2C
80
81 #ifndef CONFIG_BOOTDELAY
82 #define CONFIG_BOOTDELAY        1
83 #endif
84 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
85
86 #undef CONFIG_BOOTARGS
87 #define CONFIG_BOOTCOMMAND      "run emmcboot"
88
89 #define CONFIG_EXTRA_ENV_SETTINGS \
90         "verify=n\0"                                                    \
91         "loadaddr=0x00100000\0"                                         \
92         "console=ttyAMA2,115200n8\0"                                    \
93         "memargs256=mem=96M@0 mem_modem=32M@96M mem=30M@128M "          \
94                 "pmem=22M@158M pmem_hwb=44M@180M mem_mali=32@224M\0"    \
95         "memargs512=mem=96M@0 mem_modem=32M@96M mem=44M@128M "          \
96                 "pmem=22M@172M mem=30M@194M mem_mali=32M@224M "         \
97                 "pmem_hwb=54M@256M mem=202M@310M\0"                     \
98         "commonargs=setenv bootargs cachepolicy=writealloc noinitrd "   \
99                 "init=init "                                            \
100                 "board_id=${board_id} "                                 \
101                 "logo.${logo} "                                         \
102                 "startup_graphics=${startup_graphics}\0"                \
103         "emmcargs=setenv bootargs ${bootargs} "                         \
104                 "root=/dev/mmcblk0p2 "                                  \
105                 "rootdelay=1\0"                                         \
106         "addcons=setenv bootargs ${bootargs} "                          \
107                 "console=${console}\0"                                  \
108         "emmcboot=echo Booting from eMMC ...; "                         \
109                 "run commonargs emmcargs addcons memargs;"              \
110                 "mmc read 0 ${loadaddr} 0xA0000 0x4000;"                \
111                 "bootm ${loadaddr}\0"                                   \
112         "flash=mmc init 1;fatload mmc 1 ${loadaddr} flash.scr;"         \
113                 "source ${loadaddr}\0"                                  \
114         "loaduimage=mmc init 1;fatload mmc 1 ${loadaddr} uImage\0"      \
115         "usbtty=cdc_acm\0"                                              \
116         "stdout=serial,usbtty\0"                                        \
117         "stdin=serial,usbtty\0"                                         \
118         "stderr=serial,usbtty\0"
119
120 /*
121  * Miscellaneous configurable options
122  */
123
124 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
125 #define CONFIG_SYS_PROMPT       "U8500 $ "      /* Monitor Command Prompt   */
126 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size  */
127
128 /* Print Buffer Size */
129 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE \
130                                         + sizeof(CONFIG_SYS_PROMPT) + 16)
131 #define CONFIG_SYS_MAXARGS      32      /* max number of command args */
132 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
133
134 #undef  CONFIG_SYS_CLKS_IN_HZ           /* everything, incl board info, in Hz */
135 #define CONFIG_SYS_LOAD_ADDR            0x00100000 /* default load address */
136 #define CONFIG_SYS_LOADS_BAUD_CHANGE
137
138 #define CONFIG_SYS_HUSH_PARSER
139 #define CONFIG_CMDLINE_EDITING
140
141 #define CONFIG_SETUP_MEMORY_TAGS        2
142 #define CONFIG_INITRD_TAG
143 #define CONFIG_CMDLINE_TAG                      /* enable passing of ATAGs  */
144
145 /*
146  * I2C
147  */
148 #define CONFIG_U8500_I2C
149 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support */
150 #define CONFIG_I2C_MULTI_BUS
151 #define CONFIG_SYS_I2C_SPEED            100000
152 #define CONFIG_SYS_I2C_SLAVE            0       /* slave addr of controller */
153 #define CONFIG_SYS_U8500_I2C0_BASE              0x80004000
154 #define CONFIG_SYS_U8500_I2C1_BASE              0x80122000
155 #define CONFIG_SYS_U8500_I2C2_BASE              0x80128000
156 #define CONFIG_SYS_U8500_I2C3_BASE              0x80110000
157 #define CONFIG_SYS_U8500_I2C_BUS_MAX            4
158
159 #define CONFIG_SYS_I2C_GPIOE_ADDR       0x42    /* GPIO expander chip addr */
160 #define CONFIG_TC35892_GPIO
161
162 /*
163  * Physical Memory Map
164  */
165 #define CONFIG_NR_DRAM_BANKS            1
166 #define PHYS_SDRAM_1                    0x00000000      /* DDR-SDRAM Bank #1 */
167 #define PHYS_SDRAM_SIZE_1               0x20000000      /* 512 MB */
168
169 /*
170  * additions for new relocation code
171  */
172 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
173 #define CONFIG_SYS_INIT_RAM_SIZE        0x100000
174 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_SDRAM_BASE + \
175                                          CONFIG_SYS_INIT_RAM_SIZE - \
176                                          GENERATED_GBL_DATA_SIZE)
177 #define CONFIG_SYS_INIT_SP_ADDR         CONFIG_SYS_GBL_DATA_OFFSET
178
179 /* landing address before relocation */
180 #ifndef CONFIG_SYS_TEXT_BASE
181 #define CONFIG_SYS_TEXT_BASE            0x0
182 #endif
183
184 /*
185  * MMC related configs
186  * NB Only externa SD slot is currently supported
187  */
188 #define MMC_BLOCK_SIZE                  512
189 #define CONFIG_ARM_PL180_MMCI
190 #define CONFIG_ARM_PL180_MMCI_BASE      0x80126000      /* MMC base for 8500  */
191 #define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000
192 #define CONFIG_MMC_DEV_NUM              1
193
194 #define CONFIG_CMD_ENV
195 #define CONFIG_CMD_SAVEENV      /* CMD_ENV is obsolete but used in env_emmc.c */
196 #define CONFIG_ENV_IS_IN_MMC
197 #define CONFIG_ENV_OFFSET               0x13F80000
198 #define CONFIG_SYS_MMC_ENV_DEV          0               /* SLOT2: eMMC */
199
200 /*
201  * FLASH and environment organization
202  */
203 #define CONFIG_SYS_NO_FLASH
204
205 /*
206  * base register values for U8500
207  */
208 #define CFG_PRCMU_BASE          0x80157000      /* Power, reset and clock
209                                                    management unit */
210 #define CFG_FSMC_BASE           0x80000000      /* FSMC Controller */
211
212 #endif  /* __CONFIG_H */