include/configs/tuxa1.h

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *                    Dave Liu <daveliu@freescale.com>
   4  *
   5  * Copyright (C) 2007 Logic Product Development, Inc.
   6  *                    Peter Barada <peterb@logicpd.com>
   7  *
   8  * Copyright (C) 2007 MontaVista Software, Inc.
   9  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  10  *
  11  * (C) Copyright 2008
  12  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  13  *
  14  * (C) Copyright 2010
  15  * Yan Bin, Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
  16  *
  17  * This program is free software; you can redistribute it and/or
  18  * modify it under the terms of the GNU General Public License as
  19  * published by the Free Software Foundation; either version 2 of
  20  * the License, or (at your option) any later version.
  21  */
  22
  23 #ifndef __CONFIG_H
  24 #define __CONFIG_H
  25
  26 /*
  27  * High Level Configuration Options
  28  */
  29 #define CONFIG_QE               /* Has QE */
  30 #define CONFIG_MPC832x          /* MPC832x CPU specific */
  31 #define CONFIG_TUXA1            /* TUXA1 board specific */
  32 #define CONFIG_HOSTNAME         tuxa1
  33 #define CONFIG_KM_BOARD_NAME   "tuxa1"
  34
  35 #define CONFIG_SYS_TEXT_BASE    0xF0000000
  36 #define CONFIG_KM_DEF_NETDEV    \
  37         "netdev=eth0\0"
  38
  39 #define CONFIG_KM_DEF_ROOTPATH          \
  40         "rootpath=/opt/eldk/ppc_8xx\0"
  41
  42 /* include common defines/options for all 83xx Keymile boards */
  43 #include "km83xx-common.h"
  44
  45 #define CONFIG_MISC_INIT_R
  46
  47 /*
  48  * System IO Config
  49  */
  50 #define CONFIG_SYS_SICRL        SICRL_IRQ_CKS
  51
  52 /*
  53  * Hardware Reset Configuration Word
  54  */
  55 #define CONFIG_SYS_HRCW_LOW (\
  56         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
  57         HRCWL_DDR_TO_SCB_CLK_2X1 | \
  58         HRCWL_CSB_TO_CLKIN_2X1 | \
  59         HRCWL_CORE_TO_CSB_2_5X1 | \
  60         HRCWL_CE_PLL_VCO_DIV_2 | \
  61         HRCWL_CE_TO_PLL_1X3)
  62
  63 #define CONFIG_SYS_HRCW_HIGH (\
  64         HRCWH_PCI_AGENT | \
  65         HRCWH_PCI_ARBITER_DISABLE | \
  66         HRCWH_CORE_ENABLE | \
  67         HRCWH_FROM_0X00000100 | \
  68         HRCWH_BOOTSEQ_DISABLE | \
  69         HRCWH_SW_WATCHDOG_DISABLE | \
  70         HRCWH_ROM_LOC_LOCAL_16BIT | \
  71         HRCWH_BIG_ENDIAN | \
  72         HRCWH_LALE_NORMAL)
  73
  74 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
  75 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
  76                                          SDRAM_CFG_32_BE | \
  77                                          SDRAM_CFG_2T_EN | \
  78                                          SDRAM_CFG_SREN)
  79 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  80 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  81 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
  82                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
  83
  84 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
  85                                          CSCONFIG_ODT_WR_CFG | \
  86                                          CSCONFIG_ROW_BIT_13 | \
  87                                          CSCONFIG_COL_BIT_10)
  88
  89 #define CONFIG_SYS_DDR_MODE             0x47860252
  90 #define CONFIG_SYS_DDR_MODE2            0x8080c000
  91
  92 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
  93                                 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
  94                                 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
  95                                 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
  96                                 (0 << TIMING_CFG0_WWT_SHIFT) | \
  97                                 (0 << TIMING_CFG0_RRT_SHIFT) | \
  98                                 (0 << TIMING_CFG0_WRT_SHIFT) | \
  99                                 (0 << TIMING_CFG0_RWT_SHIFT))
 100
 101 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
 102                                 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 103                                 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 104                                 (2 << TIMING_CFG1_WRREC_SHIFT) | \
 105                                 (6 << TIMING_CFG1_REFREC_SHIFT) | \
 106                                 (2 << TIMING_CFG1_ACTTORW_SHIFT) | \
 107                                 (6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 108                                 (2 << TIMING_CFG1_PRETOACT_SHIFT))
 109
 110 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 111                                 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 112                                 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 113                                 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 114                                 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 115                                 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 116                                 (5 << TIMING_CFG2_CPO_SHIFT))
 117
 118 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 119
 120 #define CONFIG_SYS_PIGGY_BASE           0xE8000000
 121 #define CONFIG_SYS_PIGGY_SIZE           128
 122 #define CONFIG_SYS_LPXF_BASE            0xA0000000    /* LPXF */
 123 #define CONFIG_SYS_LPXF_SIZE            256 /* Megabytes */
 124 #define CONFIG_SYS_PINC2_BASE           0xB0000000    /* PINC2 */
 125 #define CONFIG_SYS_PINC2_SIZE           256 /* Megabytes */
 126
 127
 128 /* EEprom support */
 129 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 130
 131 /*
 132  * Local Bus Configuration & Clock Setup
 133  */
 134 #define CONFIG_SYS_LCRR         (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2)
 135 #define CONFIG_SYS_LBC_LBCR     0x00000000
 136
 137 /*
 138  * Init Local Bus Memory Controller:
 139  *
 140  * Bank Bus     Machine PortSz  Size  Device
 141  * ---- ---     ------- ------  -----  ------
 142  *  2   Local   GPCM    8 bit  256MB    LPXF
 143  *  3   Local   GPCM    8 bit  256MB    PINC2
 144  *
 145  */
 146
 147 /*
 148  * LPXF on the local bus CS2
 149  * Window base at flash base
 150  * Window size: 256 MB
 151  */
 152 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_LPXF_BASE
 153 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 154
 155 #define CONFIG_SYS_BR2_PRELIM       (CONFIG_SYS_LPXF_BASE | \
 156                                 BR_PS_8 | \
 157                                 BR_MS_GPCM | \
 158                                 BR_V)
 159
 160 #define CONFIG_SYS_OR2_PRELIM   (MEG_TO_AM(CONFIG_SYS_LPXF_SIZE) | \
 161                                  OR_GPCM_CSNT | \
 162                                  OR_GPCM_ACS_DIV4 | \
 163                                  OR_GPCM_SCY_2 | \
 164                                  (OR_GPCM_TRLX & \
 165                                  (~OR_GPCM_EHTR)) |  /* EHTR = 0 */ \
 166                                  OR_GPCM_EAD)
 167 /*
 168  * PINC2 on the local bus CS3
 169  * Access window base at PINC2 base
 170  * Window size: 256 MB
 171  */
 172 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_PINC2_BASE
 173 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 174
 175 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_PINC2_BASE | \
 176                                  BR_PS_8 | \
 177                                  BR_MS_GPCM | \
 178                                  BR_V)
 179
 180 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_PINC2_SIZE) | \
 181                                  OR_GPCM_CSNT | \
 182                                  (OR_GPCM_ACS_DIV2 & /* ACS = 11 */ \
 183                                  (~OR_GPCM_XACS)) |  /* XACS = 0 */ \
 184                                  (OR_GPCM_SCY_2 & \
 185                                  (~OR_GPCM_EHTR)) |  /* EHTR = 0 */ \
 186                                  OR_GPCM_TRLX)
 187
 188 #define CONFIG_SYS_MAMR         (MxMR_GPL_x4DIS | \
 189                                  0x0000c000 | \
 190                                  MxMR_WLFx_2X)
 191
 192 /*
 193  * MMU Setup
 194  */
 195 /* LPXF:  icache cacheable, but dcache-inhibit and guarded */
 196 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \
 197                                  BATL_MEMCOHERENCE)
 198 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_LPXF_BASE | BATU_BL_256M | \
 199                                  BATU_VS | BATU_VP)
 200 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \
 201                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 202 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 203
 204 #ifdef CONFIG_PCI
 205 /* PCI MEM space: cacheable */
 206 #define CFG_IBAT6L      (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
 207 #define CFG_IBAT6U      (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 208 #define CFG_DBAT6L      CFG_IBAT6L
 209 #define CFG_DBAT6U      CFG_IBAT6U
 210 /* PCI MMIO space: cache-inhibit and guarded */
 211 #define CFG_IBAT7L      (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
 212                          BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 213 #define CFG_IBAT7U      (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 214 #define CFG_DBAT7L      CFG_IBAT7L
 215 #define CFG_DBAT7U      CFG_IBAT7U
 216 #else /* CONFIG_PCI */
 217
 218 /* PINC2:  icache cacheable, but dcache-inhibit and guarded */
 219 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PINC2_BASE | BATL_PP_10 | \
 220                                  BATL_MEMCOHERENCE)
 221 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PINC2_BASE | BATU_BL_256M | \
 222                                  BATU_VS | BATU_VP)
 223 #define CONFIG_SYS_DBAT6L       (CONFIG_SYS_PINC2_BASE | BATL_PP_10 | \
 224                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 225 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 226
 227 #define CONFIG_SYS_IBAT7L       (0)
 228 #define CONFIG_SYS_IBAT7U       (0)
 229 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 230 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 231 #endif /* CONFIG_PCI */
 232
 233 #endif /* __CONFIG_H */