2 * Copyright (C) 2011 Samsung Electronics
3 * Heungjun Kim <riverful.kim@samsung.com>
5 * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * High Level Configuration Options
33 #define CONFIG_SAMSUNG /* in a SAMSUNG core */
34 #define CONFIG_S5P /* which is in a S5P Family */
35 #define CONFIG_EXYNOS4210 /* which is in a EXYNOS4210 */
36 #define CONFIG_TRATS /* working with TRATS */
37 #define CONFIG_TIZEN /* TIZEN lib */
39 #include <asm/arch/cpu.h> /* get chip and board defs */
41 #define CONFIG_ARCH_CPU_INIT
42 #define CONFIG_DISPLAY_CPUINFO
43 #define CONFIG_DISPLAY_BOARDINFO
45 #ifndef CONFIG_SYS_L2CACHE_OFF
46 #define CONFIG_SYS_L2_PL310
47 #define CONFIG_SYS_PL310_BASE 0x10502000
50 #define CONFIG_SYS_SDRAM_BASE 0x40000000
51 #define CONFIG_SYS_TEXT_BASE 0x63300000
53 /* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */
54 #define CONFIG_SYS_CLK_FREQ_C210 24000000
55 #define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210
57 #define CONFIG_SETUP_MEMORY_TAGS
58 #define CONFIG_CMDLINE_TAG
59 #define CONFIG_REVISION_TAG
60 #define CONFIG_CMDLINE_EDITING
61 #define CONFIG_SKIP_LOWLEVEL_INIT
62 #define CONFIG_BOARD_EARLY_INIT_F
64 /* MACH_TYPE_TRATS macro will be removed once added to mach-types */
65 #define MACH_TYPE_TRATS 3928
66 #define CONFIG_MACH_TYPE MACH_TYPE_TRATS
68 /* Size of malloc() pool */
69 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
71 /* select serial console configuration */
72 #define CONFIG_SERIAL_MULTI
73 #define CONFIG_SERIAL2 /* use SERIAL 2 */
74 #define CONFIG_BAUDRATE 115200
77 #define CONFIG_GENERIC_MMC
79 #define CONFIG_S5P_SDHCI
81 #define CONFIG_MMC_SDMA
86 /* It should define before config_cmd_default.h */
87 #define CONFIG_SYS_NO_FLASH
89 /* Command definition */
90 #include <config_cmd_default.h>
92 #undef CONFIG_CMD_FPGA
93 #undef CONFIG_CMD_MISC
96 #undef CONFIG_CMD_XIMG
97 #undef CONFIG_CMD_CACHE
98 #undef CONFIG_CMD_ONENAND
99 #undef CONFIG_CMD_MTDPARTS
100 #define CONFIG_CMD_MMC
101 #define CONFIG_CMD_DFU
104 #define CONFIG_CMD_FAT
105 #define CONFIG_FAT_WRITE
107 /* USB Composite download gadget - g_dnl */
108 #define CONFIG_USBDOWNLOAD_GADGET
109 #define CONFIG_DFU_FUNCTION
110 #define CONFIG_DFU_MMC
112 /* USB Samsung's IDs */
113 #define CONFIG_G_DNL_VENDOR_NUM 0x04E8
114 #define CONFIG_G_DNL_PRODUCT_NUM 0x6601
115 #define CONFIG_G_DNL_MANUFACTURER "Samsung"
117 #define CONFIG_BOOTDELAY 1
118 #define CONFIG_ZERO_BOOTDELAY_CHECK
119 #define CONFIG_BOOTARGS "Please use defined boot"
120 #define CONFIG_BOOTCOMMAND "run mmcboot"
122 #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
123 #define CONFIG_BOOTBLOCK "10"
124 #define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}"
126 #define CONFIG_DFU_ALT \
128 "u-boot mmc 80 400;" \
131 #define CONFIG_ENV_OVERWRITE
132 #define CONFIG_SYS_CONSOLE_INFO_QUIET
133 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
135 #define CONFIG_EXTRA_ENV_SETTINGS \
137 "run loaduimage; bootm 0x40007FC0\0" \
139 "mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \
140 "mmc boot 0 1 1 0\0" \
142 "mmc boot 0 1 1 2; mmc write 0 0x42100000 0 0x200;" \
143 "mmc boot 0 1 1 0\0" \
145 "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
146 "lpj=lpj=3981312\0" \
148 "set bootargs root=/dev/nfs rw " \
149 "nfsroot=${nfsroot},nolock,tcp " \
150 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
151 "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
154 "set bootargs root=/dev/ram0 rw rootfstype=ext2 " \
155 "${console} ${meminfo} " \
156 "initrd=0x43000000,8M ramdisk=8192\0" \
158 "set bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
159 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
160 "run loaduimage; bootm 0x40007FC0\0" \
161 "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
162 "boottrace=setenv opts initcall_debug; run bootcmd\0" \
163 "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
165 "rootfstype=ext4\0" \
166 "console=" CONFIG_DEFAULT_CONSOLE \
167 "meminfo=crashkernel=32M@0x50000000\0" \
168 "nfsroot=/nfsroot/arm\0" \
169 "bootblock=" CONFIG_BOOTBLOCK "\0" \
170 "loaduimage=fatload mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
174 "opts=always_resume=1\0" \
177 /* Miscellaneous configurable options */
178 #define CONFIG_SYS_LONGHELP /* undef to save memory */
179 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
180 #define CONFIG_SYS_PROMPT "TRATS # "
181 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
182 #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
183 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
184 /* Boot Argument Buffer Size */
185 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
186 /* memtest works on */
187 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
188 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
189 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
191 #define CONFIG_SYS_HZ 1000
193 /* TRATS has 2 banks of DRAM */
194 #define CONFIG_NR_DRAM_BANKS 2
195 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* LDDDR2 DMC 0 */
196 #define PHYS_SDRAM_1_SIZE (512 << 20) /* 512 MB in CS 0 */
197 #define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */
198 #define PHYS_SDRAM_2_SIZE (512 << 20) /* 512 MB in CS 0 */
200 #define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
202 #define CONFIG_SYS_MONITOR_BASE 0x00000000
203 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
205 #define CONFIG_ENV_IS_IN_MMC
206 #define CONFIG_SYS_MMC_ENV_DEV 0
207 #define CONFIG_ENV_SIZE 4096
208 #define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
210 #define CONFIG_DOS_PARTITION
212 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
213 #define CONFIG_SYS_CACHELINE_SIZE 32
216 #define CONFIG_SOFT_I2C
217 #define CONFIG_SOFT_I2C_READ_REPEATED_START
218 #define CONFIG_SYS_I2C_INIT_BOARD
219 #define CONFIG_SYS_I2C_SPEED 50000
220 #define CONFIG_I2C_MULTI_BUS
221 #define CONFIG_SOFT_I2C_MULTI_BUS
222 #define CONFIG_SYS_MAX_I2C_BUS 15
224 #include <asm/arch/gpio.h>
227 #define CONFIG_SOFT_I2C_I2C5_SCL exynos4_gpio_part1_get_nr(b, 7)
228 #define CONFIG_SOFT_I2C_I2C5_SDA exynos4_gpio_part1_get_nr(b, 6)
231 #define CONFIG_SOFT_I2C_I2C9_SCL exynos4_gpio_part2_get_nr(y4, 1)
232 #define CONFIG_SOFT_I2C_I2C9_SDA exynos4_gpio_part2_get_nr(y4, 0)
234 #define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin()
235 #define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin()
236 #define I2C_INIT multi_i2c_init()
239 #define CONFIG_PMIC_I2C
240 #define CONFIG_PMIC_MAX8997
242 #define CONFIG_USB_GADGET
243 #define CONFIG_USB_GADGET_S3C_UDC_OTG
244 #define CONFIG_USB_GADGET_DUALSPEED
245 #define CONFIG_USB_GADGET_VBUS_DRAW 2
248 #define CONFIG_EXYNOS_FB
250 #define CONFIG_CMD_BMP
251 #define CONFIG_BMP_32BPP
252 #define CONFIG_FB_ADDR 0x52504000
253 #define CONFIG_S6E8AX0
254 #define CONFIG_EXYNOS_MIPI_DSIM
255 #define CONFIG_VIDEO_BMP_GZIP
256 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 120 * 4) + (1 << 12))
258 #endif /* __CONFIG_H */