2 * (C) Copyright 2010-2012
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef _TEGRA20_COMMON_H_
9 #define _TEGRA20_COMMON_H_
10 #include "tegra-common.h"
12 /* Cortex-A9 uses a cache line size of 32 bytes */
13 #define CONFIG_SYS_CACHELINE_SIZE 32
16 * Errata configuration
18 #define CONFIG_ARM_ERRATA_716044
19 #define CONFIG_ARM_ERRATA_742230
20 #define CONFIG_ARM_ERRATA_751472
23 * NS16550 Configuration
25 #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
27 /* Environment information, boards can override if required */
28 #define CONFIG_LOADADDR 0x00408000 /* def. location for kernel */
31 * Miscellaneous configurable options
33 #define CONFIG_SYS_LOAD_ADDR 0x00A00800 /* default */
34 #define CONFIG_STACKBASE 0x02800000 /* 40MB */
36 /*-----------------------------------------------------------------------
39 #define CONFIG_SYS_TEXT_BASE 0x0010E000
42 * Memory layout for where various images get loaded by boot scripts:
44 * scriptaddr can be pretty much anywhere that doesn't conflict with something
45 * else. Put it above BOOTMAPSZ to eliminate conflicts.
47 * kernel_addr_r must be within the first 128M of RAM in order for the
48 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
49 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
50 * should not overlap that area, or the kernel will have to copy itself
51 * somewhere else before decompression. Similarly, the address of any other
52 * data passed to the kernel shouldn't overlap the start of RAM. Pushing
53 * this up to 16M allows for a sizable kernel to be decompressed below the
54 * compressed load address.
56 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
57 * the compressed kernel to be up to 16M too.
59 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
60 * for the FDT/DTB to be up to 1M, which is hopefully plenty.
62 #define MEM_LAYOUT_ENV_SETTINGS \
63 "scriptaddr=0x10000000\0" \
64 "kernel_addr_r=0x01000000\0" \
65 "fdt_addr_r=0x02000000\0" \
66 "ramdisk_addr_r=0x02100000\0"
69 #define CONFIG_SPL_TEXT_BASE 0x00108000
70 #define CONFIG_SYS_SPL_MALLOC_START 0x00090000
71 #define CONFIG_SPL_STACK 0x000ffffc
73 /* Align LCD to 1MB boundary */
74 #define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
76 #ifdef CONFIG_TEGRA_LP0
77 #define TEGRA_LP0_ADDR 0x1C406000
78 #define TEGRA_LP0_SIZE 0x2000
79 #define TEGRA_LP0_VEC \
80 "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \
81 "@" __stringify(TEGRA_LP0_ADDR) " "
87 * This parameter affects a TXFILLTUNING field that controls how much data is
88 * sent to the latency fifo before it is sent to the wire. Without this
89 * parameter, the default (2) causes occasional Data Buffer Errors in OUT
90 * packets depending on the buffer address and size.
92 #define CONFIG_USB_EHCI_TXFIFO_THRESH 10
93 #define CONFIG_EHCI_IS_TDI
94 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
96 /* Total I2C ports on Tegra20 */
97 #define TEGRA_I2C_NUM_CONTROLLERS 4
99 #define CONFIG_SYS_NAND_SELF_INIT
100 #define CONFIG_SYS_NAND_ONFI_DETECTION
102 #endif /* _TEGRA20_COMMON_H_ */