sunxi: Add support for using MII phy-s with the GMAC nic
[oweals/u-boot.git] / include / configs / taishan.h
1 /*
2  * (C) Copyright 2007
3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 /************************************************************************
9  * TAISHAN.h - configuration for AMCC 440GX Ref
10  ***********************************************************************/
11
12 #ifndef __CONFIG_H
13 #define __CONFIG_H
14
15 /*-----------------------------------------------------------------------
16  * High Level Configuration Options
17  *----------------------------------------------------------------------*/
18 #define CONFIG_TAISHAN          1       /* Board is taishan             */
19 #define CONFIG_440GX            1       /* Specifc GX support           */
20 #define CONFIG_440              1       /* ... PPC440 family            */
21 #define CONFIG_SYS_CLK_FREQ     33333333 /* external freq to pll        */
22
23 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
24
25 /*
26  * Include common defines/options for all AMCC eval boards
27  */
28 #define CONFIG_HOSTNAME         taishan
29 #define CONFIG_USE_TTY          ttyS1
30 #include "amcc-common.h"
31
32 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_pre_init          */
33 #define CONFIG_MISC_INIT_R      1       /* Call misc_init_r             */
34
35 /*-----------------------------------------------------------------------
36  * Base addresses -- Note these are effective addresses where the
37  * actual resources get mapped (not physical addresses)
38  *----------------------------------------------------------------------*/
39 #define CONFIG_SYS_FLASH_BASE           0xfc000000      /* start of FLASH       */
40 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped pci memory    */
41 #define CONFIG_SYS_ISRAM_BASE           0xc0000000      /* internal SRAM        */
42 #define CONFIG_SYS_PCI_BASE             0xd0000000      /* internal PCI regs    */
43
44 #define CONFIG_SYS_EBC0_FLASH_BASE      CONFIG_SYS_FLASH_BASE
45 #define CONFIG_SYS_EBC1_FPGA_BASE       (CONFIG_SYS_PERIPHERAL_BASE + 0x01000000)
46 #define CONFIG_SYS_EBC2_LCM_BASE        (CONFIG_SYS_PERIPHERAL_BASE + 0x02000000)
47 #define CONFIG_SYS_EBC3_CONN_BASE       (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
48
49 #define CONFIG_SYS_GPIO_BASE            (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
50
51 /*-----------------------------------------------------------------------
52  * Initial RAM & stack pointer (placed in internal SRAM)
53  *----------------------------------------------------------------------*/
54 #define CONFIG_SYS_TEMP_STACK_OCM       1
55 #define CONFIG_SYS_OCM_DATA_ADDR        CONFIG_SYS_ISRAM_BASE
56 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_ISRAM_BASE  /* Initial RAM address   */
57 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000          /* Size of used area in RAM*/
58
59 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
60 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
61
62 /*-----------------------------------------------------------------------
63  * Serial Port
64  *----------------------------------------------------------------------*/
65 #define CONFIG_CONS_INDEX       2       /* Use UART1                    */
66 #define CONFIG_SYS_EXT_SERIAL_CLOCK     (1843200 * 6)   /* Ext clk @ 11.059 MHz */
67
68 /*-----------------------------------------------------------------------
69  * Environment
70  *----------------------------------------------------------------------*/
71 #define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
72
73 /*-----------------------------------------------------------------------
74  * FLASH related
75  *----------------------------------------------------------------------*/
76 #define CONFIG_SYS_FLASH_CFI
77 #define CONFIG_FLASH_CFI_DRIVER
78 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
79 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
80
81 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
82 #define CONFIG_SYS_MAX_FLASH_BANKS     1                    /* number of banks      */
83 #define CONFIG_SYS_MAX_FLASH_SECT       1024                /* sectors per device   */
84
85 #undef  CONFIG_SYS_FLASH_CHECKSUM
86 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
87 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
88
89 #define CONFIG_ENV_SECT_SIZE    0x40000 /* size of one complete sector  */
90 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
91 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
92
93 /* Address and size of Redundant Environment Sector     */
94 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
95 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
96
97 /*-----------------------------------------------------------------------
98  * E2PROM bootstrap configure value
99  *----------------------------------------------------------------------*/
100
101 /*
102  * 800/133/66
103  * IIC 0~15: 86 78 11 6a 61 A7 04 62 00 00 00 00 00 00 00 00
104  */
105
106 /*
107  * 800/160/80
108  * IIC 0~15: 86 78 c1 a6 09 67 04 63 00 00 00 00 00 00 00 00
109  */
110
111 /*-----------------------------------------------------------------------
112  * DDR SDRAM
113  *----------------------------------------------------------------------*/
114 #undef CONFIG_SPD_EEPROM                /* Don't use SPD EEPROM for setup       */
115 #define CONFIG_SDRAM_BANK0      1       /* init onboard DDR SDRAM bank 0        */
116 #define CONFIG_SYS_SDRAM0_TR0           0xC10A401A
117 #undef CONFIG_SDRAM_ECC                 /* enable ECC support                   */
118
119 /*-----------------------------------------------------------------------
120  * I2C
121  *----------------------------------------------------------------------*/
122 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
123
124 #undef CONFIG_SYS_I2C_MULTI_EEPROMS
125 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
126 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
127 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
128 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
129
130 #define CONFIG_SYS_BOOTSTRAP_IIC_ADDR   0x50
131
132 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
133 #define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
134 #define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
135 #define CONFIG_SYS_DTT_MAX_TEMP 70
136 #define CONFIG_SYS_DTT_LOW_TEMP -30
137 #define CONFIG_SYS_DTT_HYSTERESIS       3
138
139 /*
140  * Default environment variables
141  */
142 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
143         CONFIG_AMCC_DEF_ENV                                             \
144         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
145         CONFIG_AMCC_DEF_ENV_PPC_OLD                                     \
146         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
147         "kernel_addr=fc000000\0"                                        \
148         "ramdisk_addr=fc180000\0"                                       \
149         "kozio=bootm 0xffe00000\0"                                      \
150         ""
151
152 /*-----------------------------------------------------------------------
153  * Networking
154  *----------------------------------------------------------------------*/
155 #define CONFIG_EMAC_NR_START    2       /* start with EMAC 2 (skip 0&1) */
156 #define CONFIG_PHY_ADDR         0xff         /* no phy on EMAC0         */
157 #define CONFIG_PHY1_ADDR        0xff         /* no phy on EMAC1         */
158 #define CONFIG_PHY2_ADDR        0x1
159 #define CONFIG_PHY3_ADDR        0x3
160 #define CONFIG_ET1011C_PHY      1
161 #define CONFIG_HAS_ETH0
162 #define CONFIG_HAS_ETH1
163 #define CONFIG_HAS_ETH2
164 #define CONFIG_HAS_ETH3
165 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
166 #define CONFIG_PHY_RESET        1       /* reset phy upon startup         */
167 #define CONFIG_PHY_RESET_DELAY  1000
168
169 /*
170  * Commands additional to the ones defined in amcc-common.h
171  */
172 #define CONFIG_CMD_DTT
173 #define CONFIG_CMD_PCI
174
175 /*-----------------------------------------------------------------------
176  * PCI stuff
177  *-----------------------------------------------------------------------
178  */
179 /* General PCI */
180 #define CONFIG_PCI                      /* include pci support          */
181 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
182 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
183 #define CONFIG_EEPRO100       1         /* include PCI EEPRO100         */
184 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
185 #define CONFIG_SYS_PCI_TARGBASE    0x80000000   /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
186
187 /* Board-specific PCI */
188 #define CONFIG_SYS_PCI_TARGET_INIT              /* let board init pci target    */
189
190 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8   /* AMCC */
191 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever */
192
193 #endif  /* __CONFIG_H */