2 * (C) Copyright 2000, 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific,
26 * for SinoVee Microsystems SC8xx series SBC
27 * http://www.fel.com.cn (Chinese)
28 * http://www.sinovee.com (English)
34 /* Custom configuration */
35 /* SC823,SC850,SC860SAR, FEL8xx-AT(823/850/860) */
36 /* SC85T,SC860T, FEL8xx-AT(855T/860T) */
37 /*#define CONFIG_FEL8xx_AT */
38 /*#define CONFIG_LCD */
39 /* if core > 50MHz , un-comment CONFIG_BUS_DIV2 */
40 /* #define CONFIG_50MHz */
41 /* #define CONFIG_66MHz */
42 /* #define CONFIG_75MHz */
44 /*#define CONFIG_100MHz */
45 /* #define CONFIG_BUS_DIV2 1 */
46 /* for BOOT device port size */
47 /* #define CONFIG_BOOT_8B */
48 #define CONFIG_BOOT_16B
49 /* #define CONFIG_BOOT_32B */
50 /* #define CONFIG_CAN_DRIVER */
52 #define CONFIG_FEC_ENET
54 /* #define CONFIG_SDRAM_16M */
55 #define CONFIG_SDRAM_32M
56 /* #define CONFIG_SDRAM_64M */
57 #define CFG_RESET_ADDRESS 0xffffffff
59 * High Level Configuration Options
63 /* #define CONFIG_MPC823 1 */
64 /* #define CONFIG_MPC850 1 */
65 #define CONFIG_MPC855 1
66 /* #define CONFIG_MPC860 1 */
67 /* #define CONFIG_MPC860T 1 */
69 #undef CONFIG_WATCHDOG /* watchdog */
71 #define CONFIG_SVM_SC8xx 1 /* ...on SVM SC8xx series */
73 #ifdef CONFIG_LCD /* with LCD controller ? */
74 /* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */
77 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
78 #undef CONFIG_8xx_CONS_SMC2
79 #undef CONFIG_8xx_CONS_NONE
80 #define CONFIG_BAUDRATE 19200 /* console baudrate = 115kbps */
82 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
84 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
87 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
89 #define CONFIG_BOARD_TYPES 1 /* support board types */
91 #define CONFIG_PREBOOT "echo;echo Welcome to U-Boot SVM port;echo;echo Type \"? or help\" to get on-line help;echo"
93 #undef CONFIG_BOOTARGS
94 #define CONFIG_EXTRA_ENV_SETTINGS \
95 "nfsargs=setenv bootargs root=/dev/nfs rw " \
96 "nfsroot=${serverip}:${rootpath}\0" \
97 "ramargs=setenv bootargs root=/dev/ram rw\0" \
98 "addip=setenv bootargs ${bootargs} " \
99 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
100 ":${hostname}:${netdev}:off panic=1\0" \
101 "flash_nfs=run nfsargs addip;" \
102 "bootm ${kernel_addr}\0" \
103 "flash_self=run ramargs addip;" \
104 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
105 "net_nfs=tftp 0x210000 ${bootfile};run nfsargs addip;bootm\0" \
106 "rootpath=/opt/sinovee/ppc8xx-linux-2.0/target\0" \
107 "bootfile=pImage-sc855t\0" \
108 "kernel_addr=48000000\0" \
109 "ramdisk_addr=48100000\0" \
111 #define CONFIG_BOOTCOMMAND \
112 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
113 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
114 "tftpboot 0x210000 pImage-sc855t;bootm 0x210000"
116 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
117 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
121 # undef CONFIG_STATUS_LED /* disturbs display */
123 # define CONFIG_STATUS_LED 1 /* Status LED enabled */
124 #endif /* CONFIG_LCD */
126 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
128 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
130 #define CONFIG_MAC_PARTITION
131 #define CONFIG_DOS_PARTITION
133 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
137 * Command line configuration.
139 #include <config_cmd_default.h>
141 #define CONFIG_CMD_ASKENV
142 #define CONFIG_CMD_DHCP
143 #define CONFIG_CMD_DOC
144 #define CONFIG_CMD_DATE
147 #define CFG_NAND_LEGACY
150 * Miscellaneous configurable options
152 #define CFG_LONGHELP /* undef to save memory */
153 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
155 #ifdef CFG_HUSH_PARSER
156 #define CFG_PROMPT_HUSH_PS2 "> "
159 #if defined(CONFIG_CMD_KGDB)
160 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
162 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
164 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
165 #define CFG_MAXARGS 16 /* max number of command args */
166 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
168 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
169 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
171 #define CFG_LOAD_ADDR 0x100000 /* default load address */
173 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
175 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
178 * Low Level Configuration Settings
179 * (address mappings, register initial values, etc.)
180 * You should know what you are doing if you make changes here.
182 /*-----------------------------------------------------------------------
183 * Internal Memory Mapped Register
185 #define CFG_IMMR 0xFF000000
187 /*-----------------------------------------------------------------------
188 * Definitions for initial stack pointer and data area (in DPRAM)
190 #define CFG_INIT_RAM_ADDR CFG_IMMR
191 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
192 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
193 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
194 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
196 /*-----------------------------------------------------------------------
197 * Start addresses for the final memory configuration
198 * (Set up by the startup code)
199 * Please note that CFG_SDRAM_BASE _must_ start at 0
201 #define CFG_SDRAM_BASE 0x00000000
202 #define CFG_FLASH_BASE 0x40000000
203 #define CFG_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */
204 #define CFG_MONITOR_BASE CFG_FLASH_BASE
205 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
208 * For booting Linux, the board info and command line data
209 * have to be in the first 8 MB of memory, since this is
210 * the maximum mapped by the Linux kernel during initialization.
212 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
214 /*-----------------------------------------------------------------------
217 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
218 #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
220 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
221 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
223 #define CFG_ENV_IS_IN_FLASH 1
225 #ifdef CONFIG_BOOT_8B
226 #define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
227 #define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
228 #elif defined (CONFIG_BOOT_16B)
229 #define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
230 #define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
231 #elif defined (CONFIG_BOOT_32B)
232 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
233 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
236 /* Address and size of Redundant Environment Sector */
237 #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
238 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
241 /*-----------------------------------------------------------------------
242 * Hardware Information Block
244 #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
245 #define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
246 #define CFG_HWINFO_MAGIC 0x46454C38 /* 'SVM8' */
248 /*-----------------------------------------------------------------------
249 * Cache Configuration
251 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
252 #if defined(CONFIG_CMD_KGDB)
253 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
256 /*-----------------------------------------------------------------------
257 * SYPCR - System Protection Control 11-9
258 * SYPCR can only be written once after reset!
259 *-----------------------------------------------------------------------
260 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
262 #if defined(CONFIG_WATCHDOG)
263 /*#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
264 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
266 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_SWF | \
267 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
269 #define CFG_SYPCR 0xffffff88
272 /*-----------------------------------------------------------------------
273 * SIUMCR - SIU Module Configuration 11-6
274 *-----------------------------------------------------------------------
275 * PCMCIA config., multi-function pin tri-state
277 #ifndef CONFIG_CAN_DRIVER
278 /*#define CFG_SIUMCR 0x00610c00 */
279 #define CFG_SIUMCR 0x00000000
280 #else /* we must activate GPL5 in the SIUMCR for CAN */
281 #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
282 #endif /* CONFIG_CAN_DRIVER */
284 /*-----------------------------------------------------------------------
285 * TBSCR - Time Base Status and Control 11-26
286 *-----------------------------------------------------------------------
287 * Clear Reference Interrupt Status, Timebase freezing enabled
289 #define CFG_TBSCR 0x0001
291 /*-----------------------------------------------------------------------
292 * RTCSC - Real-Time Clock Status and Control Register 11-27
293 *-----------------------------------------------------------------------
295 #define CFG_RTCSC 0x00c3
297 /*-----------------------------------------------------------------------
298 * PISCR - Periodic Interrupt Status and Control 11-31
299 *-----------------------------------------------------------------------
300 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
302 #define CFG_PISCR 0x0000
304 /*-----------------------------------------------------------------------
305 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
306 *-----------------------------------------------------------------------
307 * Reset PLL lock status sticky bit, timer expired status bit and timer
308 * interrupt status bit
310 #if defined (CONFIG_100MHz)
311 #define CFG_PLPRCR 0x06301000
312 #define CONFIG_8xx_GCLK_FREQ 100000000
313 #elif defined (CONFIG_80MHz)
314 #define CFG_PLPRCR 0x04f01000
315 #define CONFIG_8xx_GCLK_FREQ 80000000
316 #elif defined(CONFIG_75MHz)
317 #define CFG_PLPRCR 0x04a00100
318 #define CONFIG_8xx_GCLK_FREQ 75000000
319 #elif defined(CONFIG_66MHz)
320 #define CFG_PLPRCR 0x04101000
321 #define CONFIG_8xx_GCLK_FREQ 66000000
322 #elif defined(CONFIG_50MHz)
323 #define CFG_PLPRCR 0x03101000
324 #define CONFIG_8xx_GCLK_FREQ 50000000
327 /*-----------------------------------------------------------------------
328 * SCCR - System Clock and reset Control Register 15-27
329 *-----------------------------------------------------------------------
330 * Set clock output, timebase and RTC source and divider,
331 * power management and some other internal clocks
333 #define SCCR_MASK SCCR_EBDF11
334 #ifdef CONFIG_BUS_DIV2
335 #define CFG_SCCR 0x02020000 | SCCR_RTSEL
336 #else /* up to 50 MHz we use a 1:1 clock */
337 #define CFG_SCCR 0x02000000 | SCCR_RTSEL
340 /*-----------------------------------------------------------------------
342 *-----------------------------------------------------------------------
345 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
346 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
347 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
348 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
349 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
350 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
351 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
352 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
354 /*-----------------------------------------------------------------------
355 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
356 *-----------------------------------------------------------------------
359 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
361 #define CONFIG_IDE_8xx_DIRECT 1 /* Direct IDE not supported */
362 #undef CONFIG_IDE_LED /* LED for ide not supported */
363 #undef CONFIG_IDE_RESET /* reset for ide not supported */
365 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
366 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
368 #define CFG_ATA_BASE_ADDR 0xFE100010
369 #define CFG_ATA_IDE0_OFFSET 0x0000
370 /*#define CFG_ATA_IDE1_OFFSET 0x0C00 */
371 #define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O
373 #define CFG_ATA_REG_OFFSET 0x0200 /* Offset for normal register accesses
375 #define CFG_ATA_ALT_OFFSET 0x0210 /* Offset for alternate registers
378 #define CFG_PIO_MODE 0
380 /*-----------------------------------------------------------------------
382 *-----------------------------------------------------------------------
385 /*#define CFG_DER 0x2002000F*/
389 * Init Memory Controller:
391 * BR0/1 and OR0/1 (FLASH)
394 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
395 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
397 /* used to re-map FLASH both when starting from SRAM or FLASH:
398 * restrict access enough to keep SRAM working (if any)
399 * but not too much to meddle with FLASH accesses
401 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
402 #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
407 #if defined(CONFIG_100MHz)
408 #define CFG_OR_TIMING_FLASH 0x000002f4
409 #define CFG_OR_TIMING_DOC 0x000002f4
410 #define CFG_MxMR_PTx 0x61000000
411 #define CFG_MPTPR 0x400
413 #elif defined(CONFIG_80MHz)
414 #define CFG_OR_TIMING_FLASH 0x00000ff4
415 #define CFG_OR_TIMING_DOC 0x000001f4
416 #define CFG_MxMR_PTx 0x4e000000
417 #define CFG_MPTPR 0x400
419 #elif defined(CONFIG_75MHz)
420 #define CFG_OR_TIMING_FLASH 0x000008f4
421 #define CFG_OR_TIMING_DOC 0x000002f4
422 #define CFG_MxMR_PTx 0x49000000
423 #define CFG_MPTPR 0x400
425 #elif defined(CONFIG_66MHz)
426 #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
427 OR_SCY_3_CLK | OR_EHTR | OR_BI)
428 /*#define CFG_OR_TIMING_FLASH 0x000001f4 */
429 #define CFG_OR_TIMING_DOC 0x000003f4
430 #define CFG_MxMR_PTx 0x40000000
431 #define CFG_MPTPR 0x400
434 #define CFG_OR_TIMING_FLASH 0x00000ff4
435 #define CFG_OR_TIMING_DOC 0x000001f4
436 #define CFG_MxMR_PTx 0x30000000
437 #define CFG_MPTPR 0x400
438 #endif /*CONFIG_??MHz */
441 #if defined (CONFIG_BOOT_8B) /* 512K X 8 ,29F040 , 2MB space */
442 #define CFG_OR0_PRELIM (0xffe00000 | CFG_OR_TIMING_FLASH)
443 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8)
444 #elif defined (CONFIG_BOOT_16B) /* 29lv160 X 16 , 4MB space */
445 #define CFG_OR0_PRELIM (0xffc00000 | CFG_OR_TIMING_FLASH)
446 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
447 #elif defined( CONFIG_BOOT_32B ) /* 29lv160 X 2 X 32, 4/8/16MB , 64MB space */
448 #define CFG_OR0_PRELIM (0xfc000000 | CFG_OR_TIMING_FLASH)
449 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
451 #error Boot device port size missing.
455 * Disk-On-Chip configuration
458 #define CFG_DOC_SHORT_TIMEOUT
459 #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
461 #define CFG_DOC_SUPPORT_2000
462 #define CFG_DOC_SUPPORT_MILLENNIUM
463 #define CFG_DOC_BASE 0x80000000
467 * Internal Definitions
471 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
472 #define BOOTFLAG_WARM 0x02 /* Software reboot */
474 #endif /* __CONFIG_H */