include/configs/suvd3.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  *                    Dave Liu <daveliu@freescale.com>
   5  *
   6  * Copyright (C) 2007 Logic Product Development, Inc.
   7  *                    Peter Barada <peterb@logicpd.com>
   8  *
   9  * Copyright (C) 2007 MontaVista Software, Inc.
  10  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  11  *
  12  * (C) Copyright 2010
  13  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /*
  20  * High Level Configuration Options
  21  */
  22
  23 #define CONFIG_HOSTNAME         "suvd3"
  24 #define CONFIG_KM_BOARD_NAME   "suvd3"
  25
  26 /*
  27  * High Level Configuration Options
  28  */
  29 #define CONFIG_QE       /* Has QE */
  30 #define CONFIG_KM8321   /* Keymile PBEC8321 board specific */
  31
  32 #define CONFIG_KM_DEF_ARCH      "arch=ppc_8xx\0"
  33
  34 /* include common defines/options for all Keymile boards */
  35 #include "km/keymile-common.h"
  36 #include "km/km-powerpc.h"
  37
  38 /*
  39  * System Clock Setup
  40  */
  41 #define CONFIG_83XX_CLKIN               66000000
  42 #define CONFIG_SYS_CLK_FREQ             66000000
  43 #define CONFIG_83XX_PCICLK              66000000
  44
  45 /*
  46  * IMMR new address
  47  */
  48 #define CONFIG_SYS_IMMR         0xE0000000
  49
  50 /*
  51  * Bus Arbitration Configuration Register (ACR)
  52  */
  53 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
  54 #define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
  55 #define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
  56 #define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */
  57
  58 /*
  59  * DDR Setup
  60  */
  61 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  62 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  63 #define CONFIG_SYS_SDRAM_BASE2  (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
  64
  65 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  66 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  67                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  68
  69 #define CFG_83XX_DDR_USES_CS0
  70
  71 /*
  72  * Manually set up DDR parameters
  73  */
  74 #define CONFIG_DDR_II
  75 #define CONFIG_SYS_DDR_SIZE             2048 /* MB */
  76
  77 /*
  78  * The reserved memory
  79  */
  80 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  81 #define CONFIG_SYS_FLASH_BASE           0xF0000000
  82
  83 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  84 #define CONFIG_SYS_RAMBOOT
  85 #endif
  86
  87 /* Reserve 768 kB for Mon */
  88 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
  89
  90 /*
  91  * Initial RAM Base Address Setup
  92  */
  93 #define CONFIG_SYS_INIT_RAM_LOCK
  94 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
  95 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* End of used area in RAM */
  96 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
  97                                                 GENERATED_GBL_DATA_SIZE)
  98
  99 /*
 100  * Init Local Bus Memory Controller:
 101  *
 102  * Bank Bus     Machine PortSz  Size  Device
 103  * ---- ---     ------- ------  -----  ------
 104  *  0   Local   GPCM    16 bit  256MB FLASH
 105  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
 106  *
 107  */
 108 /*
 109  * FLASH on the Local Bus
 110  */
 111 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
 112
 113 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 114 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 115
 116 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | \
 117                                 BR_PS_16 | /* 16 bit port size */ \
 118                                 BR_MS_GPCM | /* MSEL = GPCM */ \
 119                                 BR_V)
 120
 121 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
 122                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 123                                 OR_GPCM_SCY_5 | \
 124                                 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 125
 126 #define CONFIG_SYS_MAX_FLASH_BANKS      1   /* max num of flash banks   */
 127 #define CONFIG_SYS_MAX_FLASH_SECT       512 /* max num of sects on one chip */
 128 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 129
 130 /*
 131  * PRIO1/PIGGY on the local bus CS1
 132  */
 133 /* Window base at flash base */
 134 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_KMBEC_FPGA_BASE
 135 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_128MB)
 136
 137 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_KMBEC_FPGA_BASE | \
 138                                 BR_PS_8 | /* 8 bit port size */ \
 139                                 BR_MS_GPCM | /* MSEL = GPCM */ \
 140                                 BR_V)
 141 #define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
 142                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 143                                 OR_GPCM_SCY_2 | \
 144                                 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 145
 146 /*
 147  * Serial Port
 148  */
 149 #define CONFIG_SYS_NS16550_SERIAL
 150 #define CONFIG_SYS_NS16550_REG_SIZE     1
 151 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 152
 153 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 154 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 155
 156 /*
 157  * QE UEC ethernet configuration
 158  */
 159 #define CONFIG_UEC_ETH
 160 #define CONFIG_ETHPRIME         "UEC0"
 161
 162 #define CONFIG_UEC_ETH1         /* GETH1 */
 163 #define UEC_VERBOSE_DEBUG       1
 164
 165 #ifdef CONFIG_UEC_ETH1
 166 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 167 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 168 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 169 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 170 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 171 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 172 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 173 #endif
 174
 175 /*
 176  * Environment
 177  */
 178
 179 #ifndef CONFIG_SYS_RAMBOOT
 180 #ifndef CONFIG_ENV_ADDR
 181 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 182                                         CONFIG_SYS_MONITOR_LEN)
 183 #endif
 184 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 185 #ifndef CONFIG_ENV_OFFSET
 186 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 187 #endif
 188
 189 /* Address and size of Redundant Environment Sector     */
 190 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 191                                                 CONFIG_ENV_SECT_SIZE)
 192 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 193
 194 #else /* CFG_SYS_RAMBOOT */
 195 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 196 #define CONFIG_ENV_SIZE         0x2000
 197 #endif /* CFG_SYS_RAMBOOT */
 198
 199 /* I2C */
 200 #define CONFIG_SYS_I2C
 201 #define CONFIG_SYS_NUM_I2C_BUSES        4
 202 #define CONFIG_SYS_I2C_MAX_HOPS         1
 203 #define CONFIG_SYS_I2C_FSL
 204 #define CONFIG_SYS_FSL_I2C_SPEED        200000
 205 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 206 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 207 #define CONFIG_SYS_I2C_OFFSET           0x3000
 208 #define CONFIG_SYS_FSL_I2C2_SPEED       200000
 209 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 210 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 211 #define CONFIG_SYS_I2C_BUSES    {{0, {I2C_NULL_HOP} }, \
 212                 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
 213                 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
 214                 {1, {I2C_NULL_HOP} } }
 215
 216 #define CONFIG_KM_IVM_BUS               2       /* I2C2 (Mux-Port 1)*/
 217
 218 #if defined(CONFIG_CMD_NAND)
 219 #define CONFIG_NAND_KMETER1
 220 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 221 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_KMBEC_FPGA_BASE
 222 #endif
 223
 224 /*
 225  * For booting Linux, the board info and command line data
 226  * have to be in the first 8 MB of memory, since this is
 227  * the maximum mapped by the Linux kernel during initialization.
 228  */
 229 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 230
 231 /*
 232  * Core HID Setup
 233  */
 234 #define CONFIG_SYS_HID0_INIT            0x000000000
 235 #define CONFIG_SYS_HID0_FINAL           (HID0_ENABLE_MACHINE_CHECK | \
 236                                          HID0_ENABLE_INSTRUCTION_CACHE)
 237 #define CONFIG_SYS_HID2                 HID2_HBE
 238
 239 /*
 240  * MMU Setup
 241  */
 242
 243 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 244
 245 /* DDR: cache cacheable */
 246 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 247                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 248 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
 249                                         BATU_VS | BATU_VP)
 250 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 251 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 252
 253 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 254 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 255                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 256 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
 257                                         | BATU_VP)
 258 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 259 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 260
 261 /* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
 262 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
 263                                 BATL_MEMCOHERENCE)
 264 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
 265                                 BATU_VS | BATU_VP)
 266 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
 267                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 268 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 269
 270 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 271 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 272                                         BATL_MEMCOHERENCE)
 273 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
 274                                         BATU_VS | BATU_VP)
 275 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 276                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 277 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 278
 279 /* Stack in dcache: cacheable, no memory coherence */
 280 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 281 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 282                                         BATU_VS | BATU_VP)
 283 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 284 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 285
 286 /*
 287  * Internal Definitions
 288  */
 289 #define BOOTFLASH_START 0xF0000000
 290
 291 #define CONFIG_KM_CONSOLE_TTY   "ttyS0"
 292
 293 /*
 294  * Environment Configuration
 295  */
 296 #define CONFIG_ENV_OVERWRITE
 297 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 298 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 299 #endif
 300
 301 #ifndef CONFIG_KM_DEF_ARCH
 302 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
 303 #endif
 304
 305 #define CONFIG_EXTRA_ENV_SETTINGS \
 306         CONFIG_KM_DEF_ENV                                               \
 307         CONFIG_KM_DEF_ARCH                                              \
 308         "newenv="                                                       \
 309                 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && "  \
 310                 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0"         \
 311         "unlock=yes\0"                                                  \
 312         ""
 313
 314 #if defined(CONFIG_UEC_ETH)
 315 #define CONFIG_HAS_ETH0
 316 #endif
 317
 318 /*
 319  * System IO Config
 320  */
 321 #define CONFIG_SYS_SICRL        SICRL_IRQ_CKS
 322
 323 /*
 324  * Hardware Reset Configuration Word
 325  */
 326 #define CONFIG_SYS_HRCW_LOW (\
 327         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
 328         HRCWL_DDR_TO_SCB_CLK_2X1 | \
 329         HRCWL_CSB_TO_CLKIN_2X1 | \
 330         HRCWL_CORE_TO_CSB_2_5X1 | \
 331         HRCWL_CE_PLL_VCO_DIV_2 | \
 332         HRCWL_CE_TO_PLL_1X3)
 333
 334 #define CONFIG_SYS_HRCW_HIGH (\
 335         HRCWH_PCI_AGENT | \
 336         HRCWH_PCI_ARBITER_DISABLE | \
 337         HRCWH_CORE_ENABLE | \
 338         HRCWH_FROM_0X00000100 | \
 339         HRCWH_BOOTSEQ_DISABLE | \
 340         HRCWH_SW_WATCHDOG_DISABLE | \
 341         HRCWH_ROM_LOC_LOCAL_16BIT | \
 342         HRCWH_BIG_ENDIAN | \
 343         HRCWH_LALE_NORMAL)
 344
 345 #define CONFIG_SYS_DDRCDR (\
 346         DDRCDR_EN | \
 347         DDRCDR_PZ_MAXZ | \
 348         DDRCDR_NZ_MAXZ | \
 349         DDRCDR_M_ODR)
 350
 351 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
 352 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 353                                          SDRAM_CFG_32_BE | \
 354                                          SDRAM_CFG_SREN | \
 355                                          SDRAM_CFG_HSE)
 356
 357 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 358 #define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 359 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 360                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
 361
 362 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 363                                          CSCONFIG_ODT_WR_CFG | \
 364                                          CSCONFIG_ROW_BIT_13 | \
 365                                          CSCONFIG_COL_BIT_10)
 366
 367 #define CONFIG_SYS_DDR_MODE     0x47860242
 368 #define CONFIG_SYS_DDR_MODE2    0x8080c000
 369
 370 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 371                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 372                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 373                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 374                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 375                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 376                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 377                                  (0 << TIMING_CFG0_RWT_SHIFT))
 378
 379 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
 380                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 381                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 382                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 383                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
 384                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 385                                  (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 386                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 387
 388 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 389                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 390                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 391                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 392                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 393                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 394                                  (5 << TIMING_CFG2_CPO_SHIFT))
 395
 396 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 397
 398 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
 399 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 400
 401 /* EEprom support */
 402 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 403
 404 /*
 405  * Local Bus Configuration & Clock Setup
 406  */
 407 #define CONFIG_SYS_LCRR_DBYP    0x80000000
 408 #define CONFIG_SYS_LCRR_EADC    0x00010000
 409 #define CONFIG_SYS_LCRR_CLKDIV  0x00000002
 410
 411 #define CONFIG_SYS_LBC_LBCR     0x00000000
 412
 413 /*
 414  * MMU Setup
 415  */
 416 #define CONFIG_SYS_IBAT7L       (0)
 417 #define CONFIG_SYS_IBAT7U       (0)
 418 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 419 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 420
 421 #define CONFIG_SYS_APP1_BASE            0xA0000000
 422 #define CONFIG_SYS_APP1_SIZE            256 /* Megabytes */
 423 #define CONFIG_SYS_APP2_BASE            0xB0000000
 424 #define CONFIG_SYS_APP2_SIZE            256 /* Megabytes */
 425
 426 /* EEprom support */
 427 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 428
 429 /*
 430  * Init Local Bus Memory Controller:
 431  *
 432  * Bank Bus     Machine PortSz  Size  Device
 433  * ---- ---     ------- ------  -----  ------
 434  *  2   Local   UPMA    16 bit  256MB APP1
 435  *  3   Local   GPCM    16 bit  256MB APP2
 436  *
 437  */
 438
 439 /*
 440  * APP1 on the local bus CS2
 441  */
 442 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_APP1_BASE
 443 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 444
 445 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_APP1_BASE | \
 446                                  BR_PS_16 | \
 447                                  BR_MS_UPMA | \
 448                                  BR_V)
 449 #define CONFIG_SYS_OR2_PRELIM   (MEG_TO_AM(CONFIG_SYS_APP1_SIZE))
 450
 451 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_APP2_BASE | \
 452                                  BR_PS_16 | \
 453                                  BR_V)
 454
 455 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
 456                                  OR_GPCM_CSNT | \
 457                                  OR_GPCM_ACS_DIV4 | \
 458                                  OR_GPCM_SCY_3 | \
 459                                  OR_GPCM_TRLX_SET)
 460
 461 #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
 462                          0x0000c000 | \
 463                          MxMR_WLFx_2X)
 464
 465 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_APP2_BASE
 466 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 467
 468 /*
 469  * MMU Setup
 470  */
 471 /* APP1:  icache cacheable, but dcache-inhibit and guarded */
 472 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
 473                                  BATL_MEMCOHERENCE)
 474 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \
 475                                  BATU_VS | BATU_VP)
 476 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
 477                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 478 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 479 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
 480                                  BATL_MEMCOHERENCE)
 481 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
 482                                  BATU_VS | BATU_VP)
 483 #define CONFIG_SYS_DBAT6L       (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
 484                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 485 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 486
 487 #endif /* __CONFIG_H */