include/configs/suvd3.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  *                    Dave Liu <daveliu@freescale.com>
   5  *
   6  * Copyright (C) 2007 Logic Product Development, Inc.
   7  *                    Peter Barada <peterb@logicpd.com>
   8  *
   9  * Copyright (C) 2007 MontaVista Software, Inc.
  10  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  11  *
  12  * (C) Copyright 2010
  13  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /*
  20  * High Level Configuration Options
  21  */
  22
  23 #define CONFIG_HOSTNAME         "suvd3"
  24 #define CONFIG_KM_BOARD_NAME   "suvd3"
  25
  26 /*
  27  * High Level Configuration Options
  28  */
  29 #define CONFIG_QE       /* Has QE */
  30 #define CONFIG_KM8321   /* Keymile PBEC8321 board specific */
  31
  32 #define CONFIG_KM_DEF_ARCH      "arch=ppc_8xx\0"
  33
  34 /* include common defines/options for all Keymile boards */
  35 #include "km/keymile-common.h"
  36 #include "km/km-powerpc.h"
  37
  38 /*
  39  * System Clock Setup
  40  */
  41 #define CONFIG_83XX_CLKIN               66000000
  42 #define CONFIG_SYS_CLK_FREQ             66000000
  43 #define CONFIG_83XX_PCICLK              66000000
  44
  45 /*
  46  * IMMR new address
  47  */
  48 #define CONFIG_SYS_IMMR         0xE0000000
  49
  50 /*
  51  * Bus Arbitration Configuration Register (ACR)
  52  */
  53 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
  54 #define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
  55 #define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
  56 #define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */
  57
  58 /*
  59  * DDR Setup
  60  */
  61 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  62 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  63 #define CONFIG_SYS_SDRAM_BASE2  (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
  64
  65 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  66 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  67                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  68
  69 #define CFG_83XX_DDR_USES_CS0
  70
  71 /*
  72  * Manually set up DDR parameters
  73  */
  74 #define CONFIG_DDR_II
  75 #define CONFIG_SYS_DDR_SIZE             2048 /* MB */
  76
  77 /*
  78  * The reserved memory
  79  */
  80 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  81 #define CONFIG_SYS_FLASH_BASE           0xF0000000
  82
  83 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  84 #define CONFIG_SYS_RAMBOOT
  85 #endif
  86
  87 /* Reserve 768 kB for Mon */
  88 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
  89
  90 /*
  91  * Initial RAM Base Address Setup
  92  */
  93 #define CONFIG_SYS_INIT_RAM_LOCK
  94 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
  95 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* End of used area in RAM */
  96 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
  97                                                 GENERATED_GBL_DATA_SIZE)
  98
  99 /*
 100  * Init Local Bus Memory Controller:
 101  *
 102  * Bank Bus     Machine PortSz  Size  Device
 103  * ---- ---     ------- ------  -----  ------
 104  *  0   Local   GPCM    16 bit  256MB FLASH
 105  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
 106  *
 107  */
 108 /*
 109  * FLASH on the Local Bus
 110  */
 111 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
 112
 113 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 114 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 115
 116 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | \
 117                                 BR_PS_16 | /* 16 bit port size */ \
 118                                 BR_MS_GPCM | /* MSEL = GPCM */ \
 119                                 BR_V)
 120
 121 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
 122                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 123                                 OR_GPCM_SCY_5 | \
 124                                 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 125
 126 #define CONFIG_SYS_MAX_FLASH_BANKS      1   /* max num of flash banks   */
 127 #define CONFIG_SYS_MAX_FLASH_SECT       512 /* max num of sects on one chip */
 128 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 129
 130 /*
 131  * PRIO1/PIGGY on the local bus CS1
 132  */
 133 /* Window base at flash base */
 134 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_KMBEC_FPGA_BASE
 135 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_128MB)
 136
 137 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_KMBEC_FPGA_BASE | \
 138                                 BR_PS_8 | /* 8 bit port size */ \
 139                                 BR_MS_GPCM | /* MSEL = GPCM */ \
 140                                 BR_V)
 141 #define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
 142                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 143                                 OR_GPCM_SCY_2 | \
 144                                 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 145
 146 /*
 147  * Serial Port
 148  */
 149 #define CONFIG_SYS_NS16550_SERIAL
 150 #define CONFIG_SYS_NS16550_REG_SIZE     1
 151 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 152
 153 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 154 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 155
 156 /*
 157  * QE UEC ethernet configuration
 158  */
 159 #define CONFIG_UEC_ETH
 160 #define CONFIG_ETHPRIME         "UEC0"
 161
 162 #define CONFIG_UEC_ETH1         /* GETH1 */
 163 #define UEC_VERBOSE_DEBUG       1
 164
 165 #ifdef CONFIG_UEC_ETH1
 166 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 167 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 168 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 169 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 170 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 171 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 172 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 173 #endif
 174
 175 /*
 176  * Environment
 177  */
 178
 179 #ifndef CONFIG_SYS_RAMBOOT
 180 #ifndef CONFIG_ENV_ADDR
 181 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 182                                         CONFIG_SYS_MONITOR_LEN)
 183 #endif
 184 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 185 #ifndef CONFIG_ENV_OFFSET
 186 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 187 #endif
 188
 189 /* Address and size of Redundant Environment Sector     */
 190 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 191                                                 CONFIG_ENV_SECT_SIZE)
 192 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 193
 194 #else /* CFG_SYS_RAMBOOT */
 195 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 196 #define CONFIG_ENV_SIZE         0x2000
 197 #endif /* CFG_SYS_RAMBOOT */
 198
 199 /* I2C */
 200 #define CONFIG_SYS_I2C
 201 #define CONFIG_SYS_NUM_I2C_BUSES        4
 202 #define CONFIG_SYS_I2C_MAX_HOPS         1
 203 #define CONFIG_SYS_I2C_FSL
 204 #define CONFIG_SYS_FSL_I2C_SPEED        200000
 205 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 206 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 207 #define CONFIG_SYS_I2C_OFFSET           0x3000
 208 #define CONFIG_SYS_FSL_I2C2_SPEED       200000
 209 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 210 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 211 #define CONFIG_SYS_I2C_BUSES    {{0, {I2C_NULL_HOP} }, \
 212                 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
 213                 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
 214                 {1, {I2C_NULL_HOP} } }
 215
 216 #define CONFIG_KM_IVM_BUS               2       /* I2C2 (Mux-Port 1)*/
 217
 218 #if defined(CONFIG_CMD_NAND)
 219 #define CONFIG_NAND_KMETER1
 220 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 221 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_KMBEC_FPGA_BASE
 222 #endif
 223
 224 /*
 225  * For booting Linux, the board info and command line data
 226  * have to be in the first 8 MB of memory, since this is
 227  * the maximum mapped by the Linux kernel during initialization.
 228  */
 229 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 230
 231 /*
 232  * Core HID Setup
 233  */
 234 #define CONFIG_SYS_HID0_INIT            0x000000000
 235 #define CONFIG_SYS_HID0_FINAL           (HID0_ENABLE_MACHINE_CHECK | \
 236                                          HID0_ENABLE_INSTRUCTION_CACHE)
 237 #define CONFIG_SYS_HID2                 HID2_HBE
 238
 239 /*
 240  * MMU Setup
 241  */
 242
 243 /* DDR: cache cacheable */
 244 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 245                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 246 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
 247                                         BATU_VS | BATU_VP)
 248 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 249 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 250
 251 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 252 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 253                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 254 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
 255                                         | BATU_VP)
 256 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 257 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 258
 259 /* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
 260 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
 261                                 BATL_MEMCOHERENCE)
 262 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
 263                                 BATU_VS | BATU_VP)
 264 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
 265                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 266 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 267
 268 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 269 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 270                                         BATL_MEMCOHERENCE)
 271 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
 272                                         BATU_VS | BATU_VP)
 273 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 274                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 275 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 276
 277 /* Stack in dcache: cacheable, no memory coherence */
 278 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 279 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 280                                         BATU_VS | BATU_VP)
 281 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 282 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 283
 284 /*
 285  * Internal Definitions
 286  */
 287 #define BOOTFLASH_START 0xF0000000
 288
 289 #define CONFIG_KM_CONSOLE_TTY   "ttyS0"
 290
 291 /*
 292  * Environment Configuration
 293  */
 294 #define CONFIG_ENV_OVERWRITE
 295 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 296 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 297 #endif
 298
 299 #ifndef CONFIG_KM_DEF_ARCH
 300 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
 301 #endif
 302
 303 #define CONFIG_EXTRA_ENV_SETTINGS \
 304         CONFIG_KM_DEF_ENV                                               \
 305         CONFIG_KM_DEF_ARCH                                              \
 306         "newenv="                                                       \
 307                 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && "  \
 308                 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0"         \
 309         "unlock=yes\0"                                                  \
 310         ""
 311
 312 #if defined(CONFIG_UEC_ETH)
 313 #define CONFIG_HAS_ETH0
 314 #endif
 315
 316 /*
 317  * System IO Config
 318  */
 319 #define CONFIG_SYS_SICRL        SICRL_IRQ_CKS
 320
 321 #define CONFIG_SYS_DDRCDR (\
 322         DDRCDR_EN | \
 323         DDRCDR_PZ_MAXZ | \
 324         DDRCDR_NZ_MAXZ | \
 325         DDRCDR_M_ODR)
 326
 327 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
 328 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 329                                          SDRAM_CFG_32_BE | \
 330                                          SDRAM_CFG_SREN | \
 331                                          SDRAM_CFG_HSE)
 332
 333 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 334 #define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 335 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 336                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
 337
 338 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 339                                          CSCONFIG_ODT_WR_CFG | \
 340                                          CSCONFIG_ROW_BIT_13 | \
 341                                          CSCONFIG_COL_BIT_10)
 342
 343 #define CONFIG_SYS_DDR_MODE     0x47860242
 344 #define CONFIG_SYS_DDR_MODE2    0x8080c000
 345
 346 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 347                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 348                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 349                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 350                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 351                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 352                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 353                                  (0 << TIMING_CFG0_RWT_SHIFT))
 354
 355 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
 356                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 357                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 358                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 359                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
 360                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 361                                  (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 362                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 363
 364 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 365                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 366                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 367                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 368                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 369                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 370                                  (5 << TIMING_CFG2_CPO_SHIFT))
 371
 372 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 373
 374 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
 375 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 376
 377 /* EEprom support */
 378 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 379
 380 /*
 381  * Local Bus Configuration & Clock Setup
 382  */
 383 #define CONFIG_SYS_LCRR_DBYP    0x80000000
 384 #define CONFIG_SYS_LCRR_EADC    0x00010000
 385 #define CONFIG_SYS_LCRR_CLKDIV  0x00000002
 386
 387 #define CONFIG_SYS_LBC_LBCR     0x00000000
 388
 389 /*
 390  * MMU Setup
 391  */
 392 #define CONFIG_SYS_IBAT7L       (0)
 393 #define CONFIG_SYS_IBAT7U       (0)
 394 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 395 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 396
 397 #define CONFIG_SYS_APP1_BASE            0xA0000000
 398 #define CONFIG_SYS_APP1_SIZE            256 /* Megabytes */
 399 #define CONFIG_SYS_APP2_BASE            0xB0000000
 400 #define CONFIG_SYS_APP2_SIZE            256 /* Megabytes */
 401
 402 /* EEprom support */
 403 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 404
 405 /*
 406  * Init Local Bus Memory Controller:
 407  *
 408  * Bank Bus     Machine PortSz  Size  Device
 409  * ---- ---     ------- ------  -----  ------
 410  *  2   Local   UPMA    16 bit  256MB APP1
 411  *  3   Local   GPCM    16 bit  256MB APP2
 412  *
 413  */
 414
 415 /*
 416  * APP1 on the local bus CS2
 417  */
 418 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_APP1_BASE
 419 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 420
 421 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_APP1_BASE | \
 422                                  BR_PS_16 | \
 423                                  BR_MS_UPMA | \
 424                                  BR_V)
 425 #define CONFIG_SYS_OR2_PRELIM   (MEG_TO_AM(CONFIG_SYS_APP1_SIZE))
 426
 427 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_APP2_BASE | \
 428                                  BR_PS_16 | \
 429                                  BR_V)
 430
 431 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
 432                                  OR_GPCM_CSNT | \
 433                                  OR_GPCM_ACS_DIV4 | \
 434                                  OR_GPCM_SCY_3 | \
 435                                  OR_GPCM_TRLX_SET)
 436
 437 #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
 438                          0x0000c000 | \
 439                          MxMR_WLFx_2X)
 440
 441 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_APP2_BASE
 442 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 443
 444 /*
 445  * MMU Setup
 446  */
 447 /* APP1:  icache cacheable, but dcache-inhibit and guarded */
 448 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
 449                                  BATL_MEMCOHERENCE)
 450 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \
 451                                  BATU_VS | BATU_VP)
 452 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
 453                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 454 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 455 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
 456                                  BATL_MEMCOHERENCE)
 457 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
 458                                  BATU_VS | BATU_VP)
 459 #define CONFIG_SYS_DBAT6L       (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
 460                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 461 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 462
 463 #endif /* __CONFIG_H */