include/configs/suvd3.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  *                    Dave Liu <daveliu@freescale.com>
   5  *
   6  * Copyright (C) 2007 Logic Product Development, Inc.
   7  *                    Peter Barada <peterb@logicpd.com>
   8  *
   9  * Copyright (C) 2007 MontaVista Software, Inc.
  10  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  11  *
  12  * (C) Copyright 2010
  13  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /*
  20  * High Level Configuration Options
  21  */
  22
  23 #define CONFIG_HOSTNAME         "suvd3"
  24 #define CONFIG_KM_BOARD_NAME   "suvd3"
  25
  26 /*
  27  * High Level Configuration Options
  28  */
  29 #define CONFIG_QE       /* Has QE */
  30 #define CONFIG_KM8321   /* Keymile PBEC8321 board specific */
  31
  32 #define CONFIG_KM_DEF_ARCH      "arch=ppc_8xx\0"
  33
  34 /* include common defines/options for all Keymile boards */
  35 #include "km/keymile-common.h"
  36 #include "km/km-powerpc.h"
  37
  38 /*
  39  * System Clock Setup
  40  */
  41 #define CONFIG_83XX_CLKIN               66000000
  42 #define CONFIG_SYS_CLK_FREQ             66000000
  43 #define CONFIG_83XX_PCICLK              66000000
  44
  45 /*
  46  * DDR Setup
  47  */
  48 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  49 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  50 #define CONFIG_SYS_SDRAM_BASE2  (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
  51
  52 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  53 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  54                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  55
  56 #define CFG_83XX_DDR_USES_CS0
  57
  58 /*
  59  * Manually set up DDR parameters
  60  */
  61 #define CONFIG_DDR_II
  62 #define CONFIG_SYS_DDR_SIZE             2048 /* MB */
  63
  64 /*
  65  * The reserved memory
  66  */
  67 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  68 #define CONFIG_SYS_FLASH_BASE           0xF0000000
  69
  70 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  71 #define CONFIG_SYS_RAMBOOT
  72 #endif
  73
  74 /* Reserve 768 kB for Mon */
  75 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
  76
  77 /*
  78  * Initial RAM Base Address Setup
  79  */
  80 #define CONFIG_SYS_INIT_RAM_LOCK
  81 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
  82 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* End of used area in RAM */
  83 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
  84                                                 GENERATED_GBL_DATA_SIZE)
  85
  86 /*
  87  * Init Local Bus Memory Controller:
  88  *
  89  * Bank Bus     Machine PortSz  Size  Device
  90  * ---- ---     ------- ------  -----  ------
  91  *  0   Local   GPCM    16 bit  256MB FLASH
  92  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
  93  *
  94  */
  95 /*
  96  * FLASH on the Local Bus
  97  */
  98 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
  99
 100
 101 #define CONFIG_SYS_MAX_FLASH_BANKS      1   /* max num of flash banks   */
 102 #define CONFIG_SYS_MAX_FLASH_SECT       512 /* max num of sects on one chip */
 103 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 104
 105 /*
 106  * PRIO1/PIGGY on the local bus CS1
 107  */
 108
 109
 110 /*
 111  * Serial Port
 112  */
 113 #define CONFIG_SYS_NS16550_SERIAL
 114 #define CONFIG_SYS_NS16550_REG_SIZE     1
 115 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 116
 117 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 118 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 119
 120 /*
 121  * QE UEC ethernet configuration
 122  */
 123 #define CONFIG_UEC_ETH
 124 #define CONFIG_ETHPRIME         "UEC0"
 125
 126 #define CONFIG_UEC_ETH1         /* GETH1 */
 127 #define UEC_VERBOSE_DEBUG       1
 128
 129 #ifdef CONFIG_UEC_ETH1
 130 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 131 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 132 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 133 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 134 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 135 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 136 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 137 #endif
 138
 139 /*
 140  * Environment
 141  */
 142
 143 #ifndef CONFIG_SYS_RAMBOOT
 144 #ifndef CONFIG_ENV_ADDR
 145 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 146                                         CONFIG_SYS_MONITOR_LEN)
 147 #endif
 148 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 149 #ifndef CONFIG_ENV_OFFSET
 150 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 151 #endif
 152
 153 /* Address and size of Redundant Environment Sector     */
 154 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 155                                                 CONFIG_ENV_SECT_SIZE)
 156 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 157
 158 #else /* CFG_SYS_RAMBOOT */
 159 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 160 #define CONFIG_ENV_SIZE         0x2000
 161 #endif /* CFG_SYS_RAMBOOT */
 162
 163 /* I2C */
 164 #define CONFIG_SYS_I2C
 165 #define CONFIG_SYS_NUM_I2C_BUSES        4
 166 #define CONFIG_SYS_I2C_MAX_HOPS         1
 167 #define CONFIG_SYS_I2C_FSL
 168 #define CONFIG_SYS_FSL_I2C_SPEED        200000
 169 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 170 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 171 #define CONFIG_SYS_I2C_OFFSET           0x3000
 172 #define CONFIG_SYS_FSL_I2C2_SPEED       200000
 173 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 174 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 175 #define CONFIG_SYS_I2C_BUSES    {{0, {I2C_NULL_HOP} }, \
 176                 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
 177                 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
 178                 {1, {I2C_NULL_HOP} } }
 179
 180 #define CONFIG_KM_IVM_BUS               2       /* I2C2 (Mux-Port 1)*/
 181
 182 #if defined(CONFIG_CMD_NAND)
 183 #define CONFIG_NAND_KMETER1
 184 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 185 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_KMBEC_FPGA_BASE
 186 #endif
 187
 188 /*
 189  * For booting Linux, the board info and command line data
 190  * have to be in the first 8 MB of memory, since this is
 191  * the maximum mapped by the Linux kernel during initialization.
 192  */
 193 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 194
 195 /*
 196  * Internal Definitions
 197  */
 198 #define BOOTFLASH_START 0xF0000000
 199
 200 #define CONFIG_KM_CONSOLE_TTY   "ttyS0"
 201
 202 /*
 203  * Environment Configuration
 204  */
 205 #define CONFIG_ENV_OVERWRITE
 206 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 207 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 208 #endif
 209
 210 #ifndef CONFIG_KM_DEF_ARCH
 211 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
 212 #endif
 213
 214 #define CONFIG_EXTRA_ENV_SETTINGS \
 215         CONFIG_KM_DEF_ENV                                               \
 216         CONFIG_KM_DEF_ARCH                                              \
 217         "newenv="                                                       \
 218                 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && "  \
 219                 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0"         \
 220         "unlock=yes\0"                                                  \
 221         ""
 222
 223 #if defined(CONFIG_UEC_ETH)
 224 #define CONFIG_HAS_ETH0
 225 #endif
 226
 227 /*
 228  * System IO Config
 229  */
 230 #define CONFIG_SYS_SICRL        SICRL_IRQ_CKS
 231
 232 #define CONFIG_SYS_DDRCDR (\
 233         DDRCDR_EN | \
 234         DDRCDR_PZ_MAXZ | \
 235         DDRCDR_NZ_MAXZ | \
 236         DDRCDR_M_ODR)
 237
 238 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
 239 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 240                                          SDRAM_CFG_32_BE | \
 241                                          SDRAM_CFG_SREN | \
 242                                          SDRAM_CFG_HSE)
 243
 244 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 245 #define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 246 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 247                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
 248
 249 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 250                                          CSCONFIG_ODT_WR_CFG | \
 251                                          CSCONFIG_ROW_BIT_13 | \
 252                                          CSCONFIG_COL_BIT_10)
 253
 254 #define CONFIG_SYS_DDR_MODE     0x47860242
 255 #define CONFIG_SYS_DDR_MODE2    0x8080c000
 256
 257 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 258                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 259                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 260                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 261                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 262                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 263                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 264                                  (0 << TIMING_CFG0_RWT_SHIFT))
 265
 266 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
 267                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 268                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 269                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 270                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
 271                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 272                                  (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 273                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 274
 275 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 276                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 277                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 278                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 279                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 280                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 281                                  (5 << TIMING_CFG2_CPO_SHIFT))
 282
 283 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 284
 285 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
 286 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 287
 288 /* EEprom support */
 289 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 290
 291 /*
 292  * Local Bus Configuration & Clock Setup
 293  */
 294 #define CONFIG_SYS_LCRR_DBYP    0x80000000
 295 #define CONFIG_SYS_LCRR_EADC    0x00010000
 296 #define CONFIG_SYS_LCRR_CLKDIV  0x00000002
 297
 298 #define CONFIG_SYS_LBC_LBCR     0x00000000
 299
 300 #define CONFIG_SYS_APP1_BASE            0xA0000000
 301 #define CONFIG_SYS_APP1_SIZE            256 /* Megabytes */
 302 #define CONFIG_SYS_APP2_BASE            0xB0000000
 303 #define CONFIG_SYS_APP2_SIZE            256 /* Megabytes */
 304
 305 /* EEprom support */
 306 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 307
 308 /*
 309  * Init Local Bus Memory Controller:
 310  *
 311  * Bank Bus     Machine PortSz  Size  Device
 312  * ---- ---     ------- ------  -----  ------
 313  *  2   Local   UPMA    16 bit  256MB APP1
 314  *  3   Local   GPCM    16 bit  256MB APP2
 315  *
 316  */
 317
 318
 319
 320 #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
 321                          0x0000c000 | \
 322                          MxMR_WLFx_2X)
 323 #endif /* __CONFIG_H */