1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
6 * Copyright (C) 2007 Logic Product Development, Inc.
7 * Peter Barada <peterb@logicpd.com>
9 * Copyright (C) 2007 MontaVista Software, Inc.
10 * Anton Vorontsov <avorontsov@ru.mvista.com>
13 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
20 * High Level Configuration Options
23 #define CONFIG_HOSTNAME "suvd3"
24 #define CONFIG_KM_BOARD_NAME "suvd3"
27 * High Level Configuration Options
29 #define CONFIG_QE /* Has QE */
30 #define CONFIG_KM8321 /* Keymile PBEC8321 board specific */
32 #define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0"
34 /* include common defines/options for all Keymile boards */
35 #include "km/keymile-common.h"
36 #include "km/km-powerpc.h"
41 #define CONFIG_83XX_CLKIN 66000000
42 #define CONFIG_SYS_CLK_FREQ 66000000
43 #define CONFIG_83XX_PCICLK 66000000
46 * Bus Arbitration Configuration Register (ACR)
48 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
49 #define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
50 #define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
51 #define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
56 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
57 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
58 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
60 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
61 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
62 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
64 #define CFG_83XX_DDR_USES_CS0
67 * Manually set up DDR parameters
70 #define CONFIG_SYS_DDR_SIZE 2048 /* MB */
75 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
76 #define CONFIG_SYS_FLASH_BASE 0xF0000000
78 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
79 #define CONFIG_SYS_RAMBOOT
82 /* Reserve 768 kB for Mon */
83 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
86 * Initial RAM Base Address Setup
88 #define CONFIG_SYS_INIT_RAM_LOCK
89 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
90 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
91 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
92 GENERATED_GBL_DATA_SIZE)
95 * Init Local Bus Memory Controller:
97 * Bank Bus Machine PortSz Size Device
98 * ---- --- ------- ------ ----- ------
99 * 0 Local GPCM 16 bit 256MB FLASH
100 * 1 Local GPCM 8 bit 128MB GPIO/PIGGY
104 * FLASH on the Local Bus
106 #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
109 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
110 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
111 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
114 * PRIO1/PIGGY on the local bus CS1
121 #define CONFIG_SYS_NS16550_SERIAL
122 #define CONFIG_SYS_NS16550_REG_SIZE 1
123 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
125 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
126 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
129 * QE UEC ethernet configuration
131 #define CONFIG_UEC_ETH
132 #define CONFIG_ETHPRIME "UEC0"
134 #define CONFIG_UEC_ETH1 /* GETH1 */
135 #define UEC_VERBOSE_DEBUG 1
137 #ifdef CONFIG_UEC_ETH1
138 #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
139 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
140 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
141 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
142 #define CONFIG_SYS_UEC1_PHY_ADDR 0
143 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
144 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
151 #ifndef CONFIG_SYS_RAMBOOT
152 #ifndef CONFIG_ENV_ADDR
153 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
154 CONFIG_SYS_MONITOR_LEN)
156 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
157 #ifndef CONFIG_ENV_OFFSET
158 #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
161 /* Address and size of Redundant Environment Sector */
162 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
163 CONFIG_ENV_SECT_SIZE)
164 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
166 #else /* CFG_SYS_RAMBOOT */
167 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
168 #define CONFIG_ENV_SIZE 0x2000
169 #endif /* CFG_SYS_RAMBOOT */
172 #define CONFIG_SYS_I2C
173 #define CONFIG_SYS_NUM_I2C_BUSES 4
174 #define CONFIG_SYS_I2C_MAX_HOPS 1
175 #define CONFIG_SYS_I2C_FSL
176 #define CONFIG_SYS_FSL_I2C_SPEED 200000
177 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
178 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
179 #define CONFIG_SYS_I2C_OFFSET 0x3000
180 #define CONFIG_SYS_FSL_I2C2_SPEED 200000
181 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
182 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
183 #define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
184 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
185 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
186 {1, {I2C_NULL_HOP} } }
188 #define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/
190 #if defined(CONFIG_CMD_NAND)
191 #define CONFIG_NAND_KMETER1
192 #define CONFIG_SYS_MAX_NAND_DEVICE 1
193 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
197 * For booting Linux, the board info and command line data
198 * have to be in the first 8 MB of memory, since this is
199 * the maximum mapped by the Linux kernel during initialization.
201 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
204 * Internal Definitions
206 #define BOOTFLASH_START 0xF0000000
208 #define CONFIG_KM_CONSOLE_TTY "ttyS0"
211 * Environment Configuration
213 #define CONFIG_ENV_OVERWRITE
214 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
215 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
218 #ifndef CONFIG_KM_DEF_ARCH
219 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
222 #define CONFIG_EXTRA_ENV_SETTINGS \
226 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \
227 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \
231 #if defined(CONFIG_UEC_ETH)
232 #define CONFIG_HAS_ETH0
238 #define CONFIG_SYS_SICRL SICRL_IRQ_CKS
240 #define CONFIG_SYS_DDRCDR (\
246 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
247 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
252 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
253 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
254 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
255 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
257 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
258 CSCONFIG_ODT_WR_CFG | \
259 CSCONFIG_ROW_BIT_13 | \
262 #define CONFIG_SYS_DDR_MODE 0x47860242
263 #define CONFIG_SYS_DDR_MODE2 0x8080c000
265 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
266 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
267 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
268 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
269 (0 << TIMING_CFG0_WWT_SHIFT) | \
270 (0 << TIMING_CFG0_RRT_SHIFT) | \
271 (0 << TIMING_CFG0_WRT_SHIFT) | \
272 (0 << TIMING_CFG0_RWT_SHIFT))
274 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
275 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
276 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
277 (3 << TIMING_CFG1_WRREC_SHIFT) | \
278 (7 << TIMING_CFG1_REFREC_SHIFT) | \
279 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
280 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
281 (3 << TIMING_CFG1_PRETOACT_SHIFT))
283 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
284 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
285 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
286 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
287 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
288 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
289 (5 << TIMING_CFG2_CPO_SHIFT))
291 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
293 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
294 #define CONFIG_SYS_KMBEC_FPGA_SIZE 128
297 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
300 * Local Bus Configuration & Clock Setup
302 #define CONFIG_SYS_LCRR_DBYP 0x80000000
303 #define CONFIG_SYS_LCRR_EADC 0x00010000
304 #define CONFIG_SYS_LCRR_CLKDIV 0x00000002
306 #define CONFIG_SYS_LBC_LBCR 0x00000000
308 #define CONFIG_SYS_APP1_BASE 0xA0000000
309 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
310 #define CONFIG_SYS_APP2_BASE 0xB0000000
311 #define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */
314 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
317 * Init Local Bus Memory Controller:
319 * Bank Bus Machine PortSz Size Device
320 * ---- --- ------- ------ ----- ------
321 * 2 Local UPMA 16 bit 256MB APP1
322 * 3 Local GPCM 16 bit 256MB APP2
328 #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
331 #endif /* __CONFIG_H */