1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
6 * Copyright (C) 2007 Logic Product Development, Inc.
7 * Peter Barada <peterb@logicpd.com>
9 * Copyright (C) 2007 MontaVista Software, Inc.
10 * Anton Vorontsov <avorontsov@ru.mvista.com>
13 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
20 * High Level Configuration Options
23 #define CONFIG_HOSTNAME "suvd3"
24 #define CONFIG_KM_BOARD_NAME "suvd3"
27 * High Level Configuration Options
29 #define CONFIG_QE /* Has QE */
30 #define CONFIG_KM8321 /* Keymile PBEC8321 board specific */
32 #define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0"
34 /* include common defines/options for all Keymile boards */
35 #include "km/keymile-common.h"
36 #include "km/km-powerpc.h"
41 #define CONFIG_83XX_CLKIN 66000000
42 #define CONFIG_SYS_CLK_FREQ 66000000
43 #define CONFIG_83XX_PCICLK 66000000
48 #define CONFIG_SYS_IMMR 0xE0000000
51 * Bus Arbitration Configuration Register (ACR)
53 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
54 #define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
55 #define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
56 #define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
61 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
62 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
63 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
65 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
66 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
67 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
69 #define CFG_83XX_DDR_USES_CS0
72 * Manually set up DDR parameters
75 #define CONFIG_SYS_DDR_SIZE 2048 /* MB */
80 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
81 #define CONFIG_SYS_FLASH_BASE 0xF0000000
83 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
84 #define CONFIG_SYS_RAMBOOT
87 /* Reserve 768 kB for Mon */
88 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
91 * Initial RAM Base Address Setup
93 #define CONFIG_SYS_INIT_RAM_LOCK
94 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
95 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
96 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
97 GENERATED_GBL_DATA_SIZE)
100 * Init Local Bus Memory Controller:
102 * Bank Bus Machine PortSz Size Device
103 * ---- --- ------- ------ ----- ------
104 * 0 Local GPCM 16 bit 256MB FLASH
105 * 1 Local GPCM 8 bit 128MB GPIO/PIGGY
109 * FLASH on the Local Bus
111 #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
114 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
115 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
116 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
119 * PRIO1/PIGGY on the local bus CS1
126 #define CONFIG_SYS_NS16550_SERIAL
127 #define CONFIG_SYS_NS16550_REG_SIZE 1
128 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
130 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
131 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
134 * QE UEC ethernet configuration
136 #define CONFIG_UEC_ETH
137 #define CONFIG_ETHPRIME "UEC0"
139 #define CONFIG_UEC_ETH1 /* GETH1 */
140 #define UEC_VERBOSE_DEBUG 1
142 #ifdef CONFIG_UEC_ETH1
143 #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
144 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
145 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
146 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
147 #define CONFIG_SYS_UEC1_PHY_ADDR 0
148 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
149 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
156 #ifndef CONFIG_SYS_RAMBOOT
157 #ifndef CONFIG_ENV_ADDR
158 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
159 CONFIG_SYS_MONITOR_LEN)
161 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
162 #ifndef CONFIG_ENV_OFFSET
163 #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
166 /* Address and size of Redundant Environment Sector */
167 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
168 CONFIG_ENV_SECT_SIZE)
169 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
171 #else /* CFG_SYS_RAMBOOT */
172 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
173 #define CONFIG_ENV_SIZE 0x2000
174 #endif /* CFG_SYS_RAMBOOT */
177 #define CONFIG_SYS_I2C
178 #define CONFIG_SYS_NUM_I2C_BUSES 4
179 #define CONFIG_SYS_I2C_MAX_HOPS 1
180 #define CONFIG_SYS_I2C_FSL
181 #define CONFIG_SYS_FSL_I2C_SPEED 200000
182 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
183 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
184 #define CONFIG_SYS_I2C_OFFSET 0x3000
185 #define CONFIG_SYS_FSL_I2C2_SPEED 200000
186 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
187 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
188 #define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
189 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
190 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
191 {1, {I2C_NULL_HOP} } }
193 #define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/
195 #if defined(CONFIG_CMD_NAND)
196 #define CONFIG_NAND_KMETER1
197 #define CONFIG_SYS_MAX_NAND_DEVICE 1
198 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
202 * For booting Linux, the board info and command line data
203 * have to be in the first 8 MB of memory, since this is
204 * the maximum mapped by the Linux kernel during initialization.
206 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
209 * Internal Definitions
211 #define BOOTFLASH_START 0xF0000000
213 #define CONFIG_KM_CONSOLE_TTY "ttyS0"
216 * Environment Configuration
218 #define CONFIG_ENV_OVERWRITE
219 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
220 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
223 #ifndef CONFIG_KM_DEF_ARCH
224 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
227 #define CONFIG_EXTRA_ENV_SETTINGS \
231 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \
232 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \
236 #if defined(CONFIG_UEC_ETH)
237 #define CONFIG_HAS_ETH0
243 #define CONFIG_SYS_SICRL SICRL_IRQ_CKS
245 #define CONFIG_SYS_DDRCDR (\
251 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
252 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
257 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
258 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
259 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
260 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
262 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
263 CSCONFIG_ODT_WR_CFG | \
264 CSCONFIG_ROW_BIT_13 | \
267 #define CONFIG_SYS_DDR_MODE 0x47860242
268 #define CONFIG_SYS_DDR_MODE2 0x8080c000
270 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
271 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
272 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
273 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
274 (0 << TIMING_CFG0_WWT_SHIFT) | \
275 (0 << TIMING_CFG0_RRT_SHIFT) | \
276 (0 << TIMING_CFG0_WRT_SHIFT) | \
277 (0 << TIMING_CFG0_RWT_SHIFT))
279 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
280 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
281 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
282 (3 << TIMING_CFG1_WRREC_SHIFT) | \
283 (7 << TIMING_CFG1_REFREC_SHIFT) | \
284 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
285 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
286 (3 << TIMING_CFG1_PRETOACT_SHIFT))
288 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
289 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
290 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
291 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
292 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
293 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
294 (5 << TIMING_CFG2_CPO_SHIFT))
296 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
298 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
299 #define CONFIG_SYS_KMBEC_FPGA_SIZE 128
302 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
305 * Local Bus Configuration & Clock Setup
307 #define CONFIG_SYS_LCRR_DBYP 0x80000000
308 #define CONFIG_SYS_LCRR_EADC 0x00010000
309 #define CONFIG_SYS_LCRR_CLKDIV 0x00000002
311 #define CONFIG_SYS_LBC_LBCR 0x00000000
313 #define CONFIG_SYS_APP1_BASE 0xA0000000
314 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
315 #define CONFIG_SYS_APP2_BASE 0xB0000000
316 #define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */
319 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
322 * Init Local Bus Memory Controller:
324 * Bank Bus Machine PortSz Size Device
325 * ---- --- ------- ------ ----- ------
326 * 2 Local UPMA 16 bit 256MB APP1
327 * 3 Local GPCM 16 bit 256MB APP2
333 #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
336 #endif /* __CONFIG_H */