2 * (C) Copyright 2005 Embedded Alley Solutions, Inc.
3 * Dan Malek <dan@embeddedalley.com>
5 * Updates for Silicon Tx GP3 SSA board.
7 * (C) Copyright 2002,2003 Motorola,Inc.
8 * Xianghua Xiao <X.Xiao@motorola.com>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 /* mpc8560ads board configuration file */
30 /* please refer to doc/README.mpc85xx for more info */
31 /* make sure you change the MAC address and other network params first,
32 * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
38 /* High Level Configuration Options */
39 #define CONFIG_BOOKE 1 /* BOOKE */
40 #define CONFIG_E500 1 /* BOOKE e500 family */
41 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
42 #define CONFIG_CPM2 1 /* has CPM2 */
43 #define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/
45 #undef CONFIG_PCI /* pci ethernet support */
46 #define CONFIG_TSEC_ENET /* tsec ethernet support*/
47 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
48 #define CONFIG_ENV_OVERWRITE
49 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
50 #undef CONFIG_DDR_ECC /* only for ECC DDR module */
51 #undef CONFIG_DDR_DLL /* possible DLL fix needed */
52 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
58 #define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
60 /* Blinkin' LEDs for Robert :-)
62 #define CONFIG_SHOW_ACTIVITY 1
65 * These can be toggled for performance analysis, otherwise use default.
67 #define CONFIG_L2_CACHE /* toggle L2 cache */
68 #define CONFIG_BTB /* toggle branch predition */
69 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
71 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
73 #undef CFG_DRAM_TEST /* memory test, takes time */
74 #define CFG_MEMTEST_START 0x00200000 /* memtest region */
75 #define CFG_MEMTEST_END 0x00400000
78 /* Localbus connector. There are many options that can be
79 * connected here, including sdram or lots of flash.
80 * This address, however, is used to configure a 256M local bus
81 * window that includes the Config latch below.
83 #define CFG_LBC_OPTION_BASE 0xf0000000 /* Localbus Extension */
84 #define CFG_LBC_OPTION_SIZE 256 /* 256MB */
86 /* There are various flash options used, we configure for the largest,
87 * which is 64Mbytes. The CFI works fine and will discover the proper
90 #define CFG_FLASH_BASE 0xfc000000 /* start of FLASH 64M */
91 #define CFG_BR0_PRELIM 0xfc001801 /* port size 32bit */
92 #define CFG_OR0_PRELIM 0xfc000ff7 /* 64 MB Flash */
94 #define CFG_FLASH_CFI 1
95 #define CFG_FLASH_CFI_DRIVER 1
96 #undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
97 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
98 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
100 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
102 #define CFG_FLASH_PROTECTION
104 /* The configuration latch is Chip Select 1.
105 * It's an 8-bit latch in the lower 8 bits of the word.
107 #define CFG_LBC_CFGLATCH_BASE 0xfb000000 /* Base of config latch */
108 #define CFG_BR1_PRELIM 0xfb001801 /* 32-bit port */
109 #define CFG_OR1_PRELIM 0xffff0ff7 /* 64K is enough */
111 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
113 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
120 #define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
122 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
124 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
125 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
133 * Base addresses -- Note these are effective addresses where the
134 * actual resources get mapped (not physical addresses)
136 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
137 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
139 #define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */
141 #undef CONFIG_CLOCKS_IN_MHZ
143 /* local bus definitions */
144 #define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
145 #define CFG_OR2_PRELIM 0xfc006901
146 #define CFG_LBC_LCRR 0x00030004 /* local bus freq */
147 #define CFG_LBC_LBCR 0x00000000
148 #define CFG_LBC_LSRT 0x20000000
149 #define CFG_LBC_MRTPR 0x20000000
150 #define CFG_LBC_LSDMR_1 0x2861b723
151 #define CFG_LBC_LSDMR_2 0x0861b723
152 #define CFG_LBC_LSDMR_3 0x0861b723
153 #define CFG_LBC_LSDMR_4 0x1861b723
154 #define CFG_LBC_LSDMR_5 0x4061b723
156 #define CONFIG_L1_INIT_RAM
157 #define CFG_INIT_RAM_LOCK 1
158 #define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
159 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
161 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
162 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
163 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
165 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
166 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
169 #define CONFIG_CONS_INDEX 2
170 #undef CONFIG_SERIAL_SOFTWARE_FIFO
172 #define CFG_NS16550_SERIAL
173 #define CFG_NS16550_REG_SIZE 1
174 #define CFG_NS16550_CLK get_bus_freq(0)
176 #define CONFIG_BAUDRATE 38400
178 #define CFG_BAUDRATE_TABLE \
179 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
181 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
182 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
184 /* Use the HUSH parser */
185 #define CFG_HUSH_PARSER
186 #ifdef CFG_HUSH_PARSER
187 #define CFG_PROMPT_HUSH_PS2 "> "
191 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
192 #define CONFIG_HARD_I2C /* I2C with hardware support*/
193 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
194 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
195 #define CFG_I2C_SLAVE 0x7F
197 #define CFG_I2C_NOPROBES {0x00} /* Don't probe these addrs */
199 /* I did the 'if 0' so we could keep the syntax above if ever needed. */
200 #undef CFG_I2C_NOPROBES
202 #define CFG_I2C_OFFSET 0x3000
204 /* I2C EEPROM. AT24C32, we keep our environment in here.
206 #define CFG_I2C_EEPROM_ADDR 0x51 /* 1010001x */
207 #define CFG_I2C_EEPROM_ADDR_LEN 2
208 #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
209 #define CFG_EEPROM_PAGE_WRITE_ENABLE
210 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
213 * Standard 8555 PCI mapping.
214 * Addresses are mapped 1-1.
216 #define CFG_PCI1_MEM_BASE 0x80000000
217 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
218 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
219 #define CFG_PCI1_IO_BASE 0x00000000
220 #define CFG_PCI1_IO_PHYS 0xe2000000
221 #define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */
223 #define CFG_PCI2_MEM_BASE 0xa0000000
224 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
225 #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
226 #define CFG_PCI2_IO_BASE 0x00000000
227 #define CFG_PCI2_IO_PHYS 0xe3000000
228 #define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */
230 #if defined(CONFIG_PCI) /* PCI Ethernet card */
232 #define CONFIG_NET_MULTI
233 #define CONFIG_PCI_PNP /* do pci plug-and-play */
235 #undef CONFIG_EEPRO100
238 #if !defined(CONFIG_PCI_PNP)
239 #define PCI_ENET0_IOADDR 0xe0000000
240 #define PCI_ENET0_MEMADDR 0xe0000000
241 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
244 #undef CONFIG_PCI_SCAN_SHOW
245 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
247 #endif /* CONFIG_PCI */
249 #if defined(CONFIG_TSEC_ENET)
251 #ifndef CONFIG_NET_MULTI
252 #define CONFIG_NET_MULTI 1
255 #define CONFIG_MII 1 /* MII PHY management */
257 #define CONFIG_MPC85XX_TSEC1 1
258 #define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
259 #define CONFIG_MPC85XX_TSEC2 1
260 #define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
261 #undef CONFIG_MPS85XX_FEC
263 #define TSEC1_PHY_ADDR 2
264 #define TSEC2_PHY_ADDR 4
265 #define TSEC1_PHYIDX 0
266 #define TSEC2_PHYIDX 0
267 #define CONFIG_ETHPRIME "TSEC0"
269 #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
271 #define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
272 #undef CONFIG_ETHER_NONE /* define if ether on something else */
273 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
275 #if (CONFIG_ETHER_INDEX == 2)
279 * - Select bus for bd/buffers
282 #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
283 #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
284 #define CFG_CPMFCR_RAMTYPE 0
286 #define CFG_FCC_PSMR (FCC_PSMR_FDE)
288 #define CFG_FCC_PSMR 0
290 #define FETH2_RST 0x01
291 #elif (CONFIG_ETHER_INDEX == 3)
292 /* need more definitions here for FE3 */
293 #define FETH3_RST 0x80
294 #endif /* CONFIG_ETHER_INDEX */
296 /* MDIO is done through the TSEC0 control.
298 #define CONFIG_MII /* MII PHY management */
299 #undef CONFIG_BITBANGMII /* bit-bang MII PHY management */
307 #define CFG_ENV_IS_IN_EEPROM 1
308 #define CFG_ENV_OFFSET 0
309 #define CFG_ENV_SIZE 2048
311 #define CFG_ENV_IS_IN_FLASH 1
312 #define CFG_ENV_SECT_SIZE 0x10000
314 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00030000)
315 #define CFG_ENV_OFFSET 0
316 #define CFG_ENV_SIZE 0x4000
319 #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400"
320 #define CONFIG_BOOTCOMMAND "bootm 0xffc00000 0xffd00000"
321 #define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
323 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
324 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
326 #if defined(CFG_RAMBOOT)
327 #if defined(CONFIG_PCI)
328 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \
329 CFG_CMD_PING | CFG_CMD_I2C) & \
332 #elif defined(CONFIG_TSEC_ENET)
333 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | \
334 CFG_CMD_MII | CFG_CMD_I2C ) & \
336 #elif defined(CONFIG_ETHER_ON_FCC)
337 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \
338 CFG_CMD_PING | CFG_CMD_I2C) & \
342 #if defined(CONFIG_PCI)
343 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \
344 CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
345 #elif defined(CONFIG_TSEC_ENET)
346 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | \
347 CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_I2C)
348 #elif defined(CONFIG_ETHER_ON_FCC)
349 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \
350 CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
353 #include <cmd_confdefs.h>
355 #undef CONFIG_WATCHDOG /* watchdog disabled */
358 * Miscellaneous configurable options
360 #define CFG_LONGHELP /* undef to save memory */
361 #define CFG_PROMPT "SSA=> " /* Monitor Command Prompt */
362 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
363 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
365 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
367 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
368 #define CFG_MAXARGS 16 /* max number of command args */
369 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
370 #define CFG_LOAD_ADDR 0x1000000 /* default load address */
371 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
374 * For booting Linux, the board info and command line data
375 * have to be in the first 8 MB of memory, since this is
376 * the maximum mapped by the Linux kernel during initialization.
378 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
380 /* Cache Configuration */
381 #define CFG_DCACHE_SIZE 32768
382 #define CFG_CACHELINE_SIZE 32
383 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
384 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
388 * Internal Definitions
392 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
393 #define BOOTFLAG_WARM 0x02 /* Software reboot */
395 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
396 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
397 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
400 /*Note: change below for your network setting!!! */
401 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
402 #define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
403 #define CONFIG_HAS_ETH1
404 #define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b
405 #define CONFIG_HAS_ETH2
406 #define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c
409 #define CONFIG_SERVERIP 192.168.85.1
410 #define CONFIG_IPADDR 192.168.85.60
411 #define CONFIG_GATEWAYIP 192.168.85.1
412 #define CONFIG_NETMASK 255.255.255.0
413 #define CONFIG_HOSTNAME STX_SSA
414 #define CONFIG_ROOTPATH /gppproot
415 #define CONFIG_BOOTFILE uImage
416 #define CONFIG_LOADADDR 0x1000000
418 #endif /* __CONFIG_H */