3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
6 * SPDX-License-Identifier: GPL-2.0+
13 * High Level Configuration Options
15 #define CONFIG_E300 1 /* E300 family */
16 #define CONFIG_MPC83xx 1 /* MPC83xx family */
17 #define CONFIG_MPC830x 1 /* MPC830x family */
18 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
19 #define CONFIG_STRIDER 1 /* STRIDER board specific */
21 #define CONFIG_SYS_TEXT_BASE 0xFE000000
23 #ifdef CONFIG_STRIDER_CPU
24 #define CONFIG_IDENT_STRING " strider cpu 0.01"
26 #define CONFIG_IDENT_STRING " strider con 0.01"
29 #define CONFIG_BOARD_EARLY_INIT_F
30 #define CONFIG_BOARD_EARLY_INIT_R
31 #define CONFIG_LAST_STAGE_INIT
34 #define CONFIG_FSL_ESDHC
35 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
36 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
38 #define CONFIG_CMD_MMC
39 #define CONFIG_GENERIC_MMC
40 #define CONFIG_DOS_PARTITION
41 #define CONFIG_CMD_EXT2
43 #define CONFIG_SYS_ALT_MEMTEST
45 #define CONFIG_CMD_FPGAD
46 #define CONFIG_CMD_IOLOOP
51 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */
52 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
55 * Hardware Reset Configuration Word
56 * if CLKIN is 66.66MHz, then
57 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
58 * We choose the A type silicon as default, so the core is 400Mhz.
60 #define CONFIG_SYS_HRCW_LOW (\
61 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
62 HRCWL_DDR_TO_SCB_CLK_2X1 |\
64 HRCWL_CSB_TO_CLKIN_4X1 |\
65 HRCWL_CORE_TO_CSB_3X1)
67 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
68 * in 8308's HRCWH according to the manual, but original Freescale's
69 * code has them and I've expirienced some problems using the board
70 * with BDI3000 attached when I've tried to set these bits to zero
71 * (UART doesn't work after the 'reset run' command).
73 #define CONFIG_SYS_HRCW_HIGH (\
75 HRCWH_PCI1_ARBITER_ENABLE |\
77 HRCWH_FROM_0XFFF00100 |\
78 HRCWH_BOOTSEQ_DISABLE |\
79 HRCWH_SW_WATCHDOG_DISABLE |\
80 HRCWH_ROM_LOC_LOCAL_16BIT |\
81 HRCWH_RL_EXT_LEGACY |\
82 HRCWH_TSEC1M_IN_MII |\
83 HRCWH_TSEC2M_IN_RGMII |\
89 #define CONFIG_SYS_SICRH (\
95 SICRH_IEEE1588_A_GPIO |\
98 SICRH_IEEE1588_B_GPIO |\
103 SICRH_TSOBI2_V2P5) /* 0x0037f103 */
104 #define CONFIG_SYS_SICRL (\
109 SICRL_ETSEC1_TX_CLK) /* 0x00000000 */
114 #define CONFIG_SYS_IMMR 0xE0000000
119 #define CONFIG_FSL_SERDES
120 #define CONFIG_FSL_SERDES1 0xe3000
125 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
126 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
127 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
132 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
133 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
134 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
135 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
136 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
143 * Manually set up DDR parameters
144 * consist of one chip NT5TU64M16HG from NANYA
147 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
149 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
150 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
151 | CSCONFIG_ODT_RD_NEVER \
152 | CSCONFIG_ODT_WR_ONLY_CURRENT \
153 | CSCONFIG_BANK_BIT_3 \
154 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
156 #define CONFIG_SYS_DDR_TIMING_3 0
157 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
158 | (0 << TIMING_CFG0_WRT_SHIFT) \
159 | (0 << TIMING_CFG0_RRT_SHIFT) \
160 | (0 << TIMING_CFG0_WWT_SHIFT) \
161 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
162 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
163 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
164 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
166 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
167 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
168 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
169 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
170 | (9 << TIMING_CFG1_REFREC_SHIFT) \
171 | (2 << TIMING_CFG1_WRREC_SHIFT) \
172 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
173 | (2 << TIMING_CFG1_WRTORD_SHIFT))
175 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
176 | (4 << TIMING_CFG2_CPO_SHIFT) \
177 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
178 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
179 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
180 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
181 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
183 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
184 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
186 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
187 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
191 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
192 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
193 | (0x0242 << SDRAM_MODE_SD_SHIFT))
194 /* ODT 150ohm CL=4, AL=0 on SDRAM */
195 #define CONFIG_SYS_DDR_MODE2 0x00000000
200 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
201 #define CONFIG_SYS_MEMTEST_END 0x07f00000
204 * The reserved memory
206 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
208 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
209 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
212 * Initial RAM Base Address Setup
214 #define CONFIG_SYS_INIT_RAM_LOCK 1
215 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
216 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
217 #define CONFIG_SYS_GBL_DATA_OFFSET \
218 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
221 * Local Bus Configuration & Clock Setup
223 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
224 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
225 #define CONFIG_SYS_LBC_LBCR 0x00040000
228 * FLASH on the Local Bus
231 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
232 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
233 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
234 #define CONFIG_FLASH_CFI_LEGACY
235 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
237 #define CONFIG_SYS_NO_FLASH
240 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
241 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
242 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
244 /* Window base at flash base */
245 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
246 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
248 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
249 | BR_PS_16 /* 16 bit port */ \
250 | BR_MS_GPCM /* MSEL = GPCM */ \
252 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
261 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
262 #define CONFIG_SYS_MAX_FLASH_SECT 135
264 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
265 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
270 #define CONFIG_SYS_FPGA0_BASE 0xE0600000
271 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
273 /* Window base at FPGA base */
274 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE
275 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB)
277 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \
278 | BR_PS_16 /* 16 bit port */ \
279 | BR_MS_GPCM /* MSEL = GPCM */ \
282 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
286 | OR_GPCM_TRLX_CLEAR \
287 | OR_GPCM_EHTR_CLEAR)
289 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
290 #define CONFIG_SYS_FPGA_DONE(k) 0x0010
292 #define CONFIG_SYS_FPGA_COUNT 1
294 #define CONFIG_SYS_MCLINK_MAX 3
296 #define CONFIG_SYS_FPGA_PTR \
297 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
299 #define CONFIG_SYS_FPGA_NO_RFL_HI
304 #define CONFIG_CONS_INDEX 2
305 #define CONFIG_SYS_NS16550_SERIAL
306 #define CONFIG_SYS_NS16550_REG_SIZE 1
307 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
309 #define CONFIG_SYS_BAUDRATE_TABLE \
310 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
312 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
313 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
315 /* Pass open firmware flat tree */
318 #define CONFIG_SYS_I2C
319 #define CONFIG_SYS_I2C_FSL
320 #define CONFIG_SYS_FSL_I2C_SPEED 400000
321 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
322 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
324 #define CONFIG_PCA953X /* NXP PCA9554 */
325 #define CONFIG_CMD_PCA953X
326 #define CONFIG_CMD_PCA953X_INFO
327 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \
328 {0x3c, 8}, {0x3d, 8}, {0x3e, 8} }
330 #define CONFIG_PCA9698 /* NXP PCA9698 */
332 #define CONFIG_SYS_I2C_IHS
333 #define CONFIG_SYS_I2C_IHS_CH0
334 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000
335 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
336 #define CONFIG_SYS_I2C_IHS_CH1
337 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000
338 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
339 #define CONFIG_SYS_I2C_IHS_CH2
340 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000
341 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
342 #define CONFIG_SYS_I2C_IHS_CH3
343 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000
344 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
347 * Software (bit-bang) I2C driver configuration
349 #define CONFIG_SYS_I2C_SOFT
350 #define CONFIG_SOFT_I2C_READ_REPEATED_START
351 #define CONFIG_SYS_I2C_SOFT_SPEED 50000
352 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
353 #define I2C_SOFT_DECLARATIONS2
354 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
355 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
356 #define I2C_SOFT_DECLARATIONS3
357 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
358 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
359 #define I2C_SOFT_DECLARATIONS4
360 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
361 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
362 #ifdef CONFIG_STRIDER_CON
363 #define I2C_SOFT_DECLARATIONS5
364 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
365 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
366 #define I2C_SOFT_DECLARATIONS6
367 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
368 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
369 #define I2C_SOFT_DECLARATIONS7
370 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
371 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
372 #define I2C_SOFT_DECLARATIONS8
373 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
374 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
377 #ifdef CONFIG_STRIDER_CON
378 #define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
379 #define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
380 #define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8}
381 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
382 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
385 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
386 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
387 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
388 #define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \
393 void fpga_gpio_set(unsigned int bus, int pin);
394 void fpga_gpio_clear(unsigned int bus, int pin);
395 int fpga_gpio_get(unsigned int bus, int pin);
398 #ifdef CONFIG_STRIDER_CON
399 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040)
400 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
401 #define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \
402 (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR)
404 #define I2C_SDA_GPIO 0x0040
405 #define I2C_SCL_GPIO 0x0020
406 #define I2C_FPGA_IDX I2C_ADAP_HWNR
408 #define I2C_ACTIVE { }
409 #define I2C_TRISTATE { }
411 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
412 #define I2C_SDA(bit) \
415 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
417 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
419 #define I2C_SCL(bit) \
422 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
424 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
426 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
429 * Software (bit-bang) MII driver configuration
431 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
432 #define CONFIG_BITBANGMII_MULTI
437 #define CONFIG_SYS_OSD_SCREENS 1
438 #define CONFIG_SYS_DP501_DIFFERENTIAL
439 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
443 * Addresses are mapped 1-1.
445 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
446 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
447 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
448 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
449 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
450 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
451 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
452 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
453 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
455 /* enable PCIE clock */
456 #define CONFIG_SYS_SCCR_PCIEXP1CM 1
459 #define CONFIG_PCI_INDIRECT_BRIDGE
462 #define CONFIG_PCI_PNP /* do pci plug-and-play */
464 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
465 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
470 #define CONFIG_TSEC_ENET /* TSEC ethernet support */
471 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
472 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
475 * TSEC ethernet configuration
477 #define CONFIG_MII 1 /* MII PHY management */
479 #define CONFIG_TSEC1_NAME "eTSEC0"
480 #define TSEC1_PHY_ADDR 1
481 #define TSEC1_PHYIDX 0
482 #define TSEC1_FLAGS 0
484 /* Options are: eTSEC[0-1] */
485 #define CONFIG_ETHPRIME "eTSEC0"
491 #define CONFIG_ENV_IS_IN_FLASH 1
492 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
493 CONFIG_SYS_MONITOR_LEN)
494 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
495 #define CONFIG_ENV_SIZE 0x2000
496 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
497 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
499 #define CONFIG_ENV_IS_NOWHERE
500 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
503 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
504 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
507 * Command line configuration.
509 #define CONFIG_CMD_MII
510 #define CONFIG_CMD_PCI
512 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
513 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
516 * Miscellaneous configurable options
518 #define CONFIG_SYS_LONGHELP /* undef to save memory */
519 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
520 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
522 #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
524 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
526 #define CONFIG_SYS_CONSOLE_INFO_QUIET
528 /* Print Buffer Size */
529 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
530 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
531 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
534 * For booting Linux, the board info and command line data
535 * have to be in the first 256 MB of memory, since this is
536 * the maximum mapped by the Linux kernel during initialization.
538 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
543 #define CONFIG_SYS_HID0_INIT 0x000000000
544 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
545 HID0_ENABLE_INSTRUCTION_CACHE | \
546 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
547 #define CONFIG_SYS_HID2 HID2_HBE
553 /* DDR: cache cacheable */
554 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
556 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
558 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
559 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
561 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
562 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
563 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
564 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
566 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
567 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
569 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
570 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
572 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
574 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
575 BATL_CACHEINHIBIT | \
577 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
579 /* Stack in dcache: cacheable, no memory coherence */
580 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
581 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
583 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
584 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
587 * Environment Configuration
590 #define CONFIG_ENV_OVERWRITE
592 #if defined(CONFIG_TSEC_ENET)
593 #define CONFIG_HAS_ETH0
596 #define CONFIG_BAUDRATE 115200
598 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
600 #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
602 #define CONFIG_HOSTNAME hrcon
603 #define CONFIG_ROOTPATH "/opt/nfsroot"
604 #define CONFIG_BOOTFILE "uImage"
606 #define CONFIG_PREBOOT /* enable preboot variable */
608 #define CONFIG_EXTRA_ENV_SETTINGS \
610 "consoledev=ttyS1\0" \
611 "u-boot=u-boot.bin\0" \
612 "kernel_addr=1000000\0" \
613 "fdt_addr=C00000\0" \
614 "fdtfile=hrcon.dtb\0" \
615 "load=tftp ${loadaddr} ${u-boot}\0" \
616 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
617 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
618 " +${filesize};cp.b ${fileaddr} " \
619 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
620 "upd=run load update\0" \
622 #define CONFIG_NFSBOOTCOMMAND \
623 "setenv bootargs root=/dev/nfs rw " \
624 "nfsroot=$serverip:$rootpath " \
625 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
626 "console=$consoledev,$baudrate $othbootargs;" \
627 "tftp ${kernel_addr} $bootfile;" \
628 "tftp ${fdt_addr} $fdtfile;" \
629 "bootm ${kernel_addr} - ${fdt_addr}"
631 #define CONFIG_MMCBOOTCOMMAND \
632 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
633 "console=$consoledev,$baudrate $othbootargs;" \
634 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
635 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
636 "bootm ${kernel_addr} - ${fdt_addr}"
638 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
640 #endif /* __CONFIG_H */