1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
12 * High Level Configuration Options
14 #define CONFIG_E300 1 /* E300 family */
16 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
21 #define CONFIG_SYS_SICRH (\
27 SICRH_IEEE1588_A_GPIO |\
30 SICRH_IEEE1588_B_GPIO |\
35 SICRH_TSOBI2_V2P5) /* 0x0037f103 */
36 #define CONFIG_SYS_SICRL (\
41 SICRL_ETSEC1_TX_CLK) /* 0x00000000 */
46 #define CONFIG_SYS_IMMR 0xE0000000
51 #define CONFIG_FSL_SERDES
52 #define CONFIG_FSL_SERDES1 0xe3000
57 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
58 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
59 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
64 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
65 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
66 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
67 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
68 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
75 * Manually set up DDR parameters
76 * consist of one chip NT5TU64M16HG from NANYA
79 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
81 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
82 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
83 | CSCONFIG_ODT_RD_NEVER \
84 | CSCONFIG_ODT_WR_ONLY_CURRENT \
85 | CSCONFIG_BANK_BIT_3 \
86 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
88 #define CONFIG_SYS_DDR_TIMING_3 0
89 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
90 | (0 << TIMING_CFG0_WRT_SHIFT) \
91 | (0 << TIMING_CFG0_RRT_SHIFT) \
92 | (0 << TIMING_CFG0_WWT_SHIFT) \
93 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
94 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
95 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
96 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
98 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
99 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
100 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
101 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
102 | (9 << TIMING_CFG1_REFREC_SHIFT) \
103 | (2 << TIMING_CFG1_WRREC_SHIFT) \
104 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
105 | (2 << TIMING_CFG1_WRTORD_SHIFT))
107 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
108 | (4 << TIMING_CFG2_CPO_SHIFT) \
109 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
110 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
111 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
112 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
113 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
115 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
116 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
118 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
119 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
123 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
124 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
125 | (0x0242 << SDRAM_MODE_SD_SHIFT))
126 /* ODT 150ohm CL=4, AL=0 on SDRAM */
127 #define CONFIG_SYS_DDR_MODE2 0x00000000
132 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
133 #define CONFIG_SYS_MEMTEST_END 0x07f00000
136 * The reserved memory
138 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
140 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
141 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
144 * Initial RAM Base Address Setup
146 #define CONFIG_SYS_INIT_RAM_LOCK 1
147 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
148 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
149 #define CONFIG_SYS_GBL_DATA_OFFSET \
150 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
153 * Local Bus Configuration & Clock Setup
155 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
156 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
157 #define CONFIG_SYS_LBC_LBCR 0x00040000
160 * FLASH on the Local Bus
162 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
163 #define CONFIG_FLASH_CFI_LEGACY
164 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
166 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
167 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
170 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
171 #define CONFIG_SYS_MAX_FLASH_SECT 135
173 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
174 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
179 #define CONFIG_SYS_FPGA0_BASE 0xE0600000
180 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
183 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
184 #define CONFIG_SYS_FPGA_DONE(k) 0x0010
186 #define CONFIG_SYS_FPGA_COUNT 1
188 #define CONFIG_SYS_MCLINK_MAX 3
190 #define CONFIG_SYS_FPGA_PTR \
191 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
193 #define CONFIG_SYS_FPGA_NO_RFL_HI
198 #define CONFIG_SYS_NS16550_SERIAL
199 #define CONFIG_SYS_NS16550_REG_SIZE 1
200 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
202 #define CONFIG_SYS_BAUDRATE_TABLE \
203 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
205 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
206 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
208 /* Pass open firmware flat tree */
211 #define CONFIG_SYS_I2C
212 #define CONFIG_SYS_I2C_FSL
213 #define CONFIG_SYS_FSL_I2C_SPEED 400000
214 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
215 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
217 #define CONFIG_PCA953X /* NXP PCA9554 */
218 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \
219 {0x3c, 8}, {0x3d, 8}, {0x3e, 8} }
221 #define CONFIG_PCA9698 /* NXP PCA9698 */
223 #define CONFIG_SYS_I2C_IHS
224 #define CONFIG_SYS_I2C_IHS_CH0
225 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000
226 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
227 #define CONFIG_SYS_I2C_IHS_CH1
228 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000
229 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
230 #define CONFIG_SYS_I2C_IHS_CH2
231 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000
232 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
233 #define CONFIG_SYS_I2C_IHS_CH3
234 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000
235 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
237 #ifdef CONFIG_STRIDER_CON_DP
238 #define CONFIG_SYS_I2C_IHS_DUAL
239 #define CONFIG_SYS_I2C_IHS_CH0_1
240 #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
241 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
242 #define CONFIG_SYS_I2C_IHS_CH1_1
243 #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
244 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
245 #define CONFIG_SYS_I2C_IHS_CH2_1
246 #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000
247 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
248 #define CONFIG_SYS_I2C_IHS_CH3_1
249 #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000
250 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
254 * Software (bit-bang) I2C driver configuration
256 #define CONFIG_SYS_I2C_SOFT
257 #define CONFIG_SOFT_I2C_READ_REPEATED_START
258 #define CONFIG_SYS_I2C_SOFT_SPEED 50000
259 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
260 #define I2C_SOFT_DECLARATIONS2
261 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
262 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
263 #define I2C_SOFT_DECLARATIONS3
264 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
265 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
266 #define I2C_SOFT_DECLARATIONS4
267 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
268 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
269 #if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP)
270 #define I2C_SOFT_DECLARATIONS5
271 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
272 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
273 #define I2C_SOFT_DECLARATIONS6
274 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
275 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
276 #define I2C_SOFT_DECLARATIONS7
277 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
278 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
279 #define I2C_SOFT_DECLARATIONS8
280 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
281 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
283 #ifdef CONFIG_STRIDER_CON_DP
284 #define I2C_SOFT_DECLARATIONS9
285 #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000
286 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
287 #define I2C_SOFT_DECLARATIONS10
288 #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000
289 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
290 #define I2C_SOFT_DECLARATIONS11
291 #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000
292 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
293 #define I2C_SOFT_DECLARATIONS12
294 #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000
295 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
298 #ifdef CONFIG_STRIDER_CON
299 #define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
300 #define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
301 #define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8}
302 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
303 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
305 #elif defined(CONFIG_STRIDER_CON_DP)
306 #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20}
307 #define CONFIG_SYS_CH7301_I2C {1, 3, 5, 7}
308 #define CONFIG_SYS_ADV7611_I2C {1, 3, 5, 7}
309 #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8}
310 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
312 #elif defined(CONFIG_STRIDER_CPU_DP)
313 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
314 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
315 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
316 #define CONFIG_STRIDER_FANS { {6, 0x4c}, {7, 0x4c}, \
319 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
320 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
321 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
322 #define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \
327 void fpga_gpio_set(unsigned int bus, int pin);
328 void fpga_gpio_clear(unsigned int bus, int pin);
329 int fpga_gpio_get(unsigned int bus, int pin);
330 void fpga_control_set(unsigned int bus, int pin);
331 void fpga_control_clear(unsigned int bus, int pin);
334 #ifdef CONFIG_STRIDER_CON
335 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040)
336 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
337 #define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \
338 (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR)
339 #elif defined(CONFIG_STRIDER_CON_DP)
340 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
341 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
342 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4)
344 #define I2C_SDA_GPIO 0x0040
345 #define I2C_SCL_GPIO 0x0020
346 #define I2C_FPGA_IDX I2C_ADAP_HWNR
349 #ifdef CONFIG_STRIDER_CON_DP
352 if (I2C_ADAP_HWNR > 7) \
353 fpga_control_set(I2C_FPGA_IDX, 0x0004); \
355 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
358 #define I2C_ACTIVE { }
361 #define I2C_TRISTATE { }
363 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
364 #define I2C_SDA(bit) \
367 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
369 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
371 #define I2C_SCL(bit) \
374 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
376 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
378 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
381 * Software (bit-bang) MII driver configuration
383 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
384 #define CONFIG_BITBANGMII_MULTI
389 #define CONFIG_SYS_OSD_SCREENS 1
390 #define CONFIG_SYS_DP501_DIFFERENTIAL
391 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
393 #ifdef CONFIG_STRIDER_CON_DP
394 #define CONFIG_SYS_OSD_DH
399 * Addresses are mapped 1-1.
401 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
402 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
403 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
404 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
405 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
406 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
407 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
408 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
409 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
411 /* enable PCIE clock */
412 #define CONFIG_SYS_SCCR_PCIEXP1CM 1
414 #define CONFIG_PCI_INDIRECT_BRIDGE
417 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
418 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
423 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
424 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
427 * TSEC ethernet configuration
430 #define CONFIG_TSEC1_NAME "eTSEC0"
431 #define TSEC1_PHY_ADDR 1
432 #define TSEC1_PHYIDX 0
433 #define TSEC1_FLAGS 0
435 /* Options are: eTSEC[0-1] */
436 #define CONFIG_ETHPRIME "eTSEC0"
442 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
443 CONFIG_SYS_MONITOR_LEN)
444 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
445 #define CONFIG_ENV_SIZE 0x2000
446 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
447 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
449 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
452 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
453 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
456 * Command line configuration.
460 * Miscellaneous configurable options
462 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
463 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
465 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
467 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
470 * For booting Linux, the board info and command line data
471 * have to be in the first 256 MB of memory, since this is
472 * the maximum mapped by the Linux kernel during initialization.
474 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
477 * Environment Configuration
480 #define CONFIG_ENV_OVERWRITE
482 #if defined(CONFIG_TSEC_ENET)
483 #define CONFIG_HAS_ETH0
486 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
489 #define CONFIG_HOSTNAME "hrcon"
490 #define CONFIG_ROOTPATH "/opt/nfsroot"
491 #define CONFIG_BOOTFILE "uImage"
493 #define CONFIG_PREBOOT /* enable preboot variable */
495 #define CONFIG_EXTRA_ENV_SETTINGS \
497 "consoledev=ttyS1\0" \
498 "u-boot=u-boot.bin\0" \
499 "kernel_addr=1000000\0" \
500 "fdt_addr=C00000\0" \
501 "fdtfile=hrcon.dtb\0" \
502 "load=tftp ${loadaddr} ${u-boot}\0" \
503 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
504 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
505 " +${filesize};cp.b ${fileaddr} " \
506 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
507 "upd=run load update\0" \
509 #define CONFIG_NFSBOOTCOMMAND \
510 "setenv bootargs root=/dev/nfs rw " \
511 "nfsroot=$serverip:$rootpath " \
512 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
513 "console=$consoledev,$baudrate $othbootargs;" \
514 "tftp ${kernel_addr} $bootfile;" \
515 "tftp ${fdt_addr} $fdtfile;" \
516 "bootm ${kernel_addr} - ${fdt_addr}"
518 #define CONFIG_MMCBOOTCOMMAND \
519 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
520 "console=$consoledev,$baudrate $othbootargs;" \
521 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
522 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
523 "bootm ${kernel_addr} - ${fdt_addr}"
525 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
527 #endif /* __CONFIG_H */