include/configs/strider.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2014
   4  * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
   5  *
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  */
  14 #define CONFIG_E300             1 /* E300 family */
  15
  16 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
  17
  18 /*
  19  * SERDES
  20  */
  21 #define CONFIG_FSL_SERDES
  22 #define CONFIG_FSL_SERDES1      0xe3000
  23
  24 /*
  25  * DDR Setup
  26  */
  27 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  28 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  29 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  30 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  31 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  32                                 | DDRCDR_PZ_LOZ \
  33                                 | DDRCDR_NZ_LOZ \
  34                                 | DDRCDR_ODT \
  35                                 | DDRCDR_Q_DRN)
  36                                 /* 0x7b880001 */
  37 /*
  38  * Manually set up DDR parameters
  39  * consist of one chip NT5TU64M16HG from NANYA
  40  */
  41
  42 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
  43
  44 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
  45 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  46                                 | CSCONFIG_ODT_RD_NEVER \
  47                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
  48                                 | CSCONFIG_BANK_BIT_3 \
  49                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
  50                                 /* 0x80010102 */
  51 #define CONFIG_SYS_DDR_TIMING_3 0
  52 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  53                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  54                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  55                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  56                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  57                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  58                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  59                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  60                                 /* 0x00260802 */
  61 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  62                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  63                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  64                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
  65                                 | (9 << TIMING_CFG1_REFREC_SHIFT) \
  66                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
  67                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  68                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  69                                 /* 0x26279222 */
  70 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
  71                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
  72                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  73                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  74                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  75                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  76                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
  77                                 /* 0x021848c5 */
  78 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
  79                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  80                                 /* 0x08240100 */
  81 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
  82                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  83                                 | SDRAM_CFG_DBW_16)
  84                                 /* 0x43100000 */
  85
  86 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
  87 #define CONFIG_SYS_DDR_MODE             ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
  88                                 | (0x0242 << SDRAM_MODE_SD_SHIFT))
  89                                 /* ODT 150ohm CL=4, AL=0 on SDRAM */
  90 #define CONFIG_SYS_DDR_MODE2            0x00000000
  91
  92 /*
  93  * Memory test
  94  */
  95 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
  96 #define CONFIG_SYS_MEMTEST_END          0x07f00000
  97
  98 /*
  99  * The reserved memory
 100  */
 101 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 102
 103 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 104 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 105
 106 /*
 107  * Initial RAM Base Address Setup
 108  */
 109 #define CONFIG_SYS_INIT_RAM_LOCK        1
 110 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 111 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 112 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 113         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 114
 115 /*
 116  * Local Bus Configuration & Clock Setup
 117  */
 118 #define CONFIG_SYS_LBC_LBCR             0x00040000
 119
 120 /*
 121  * FLASH on the Local Bus
 122  */
 123 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 124 #define CONFIG_FLASH_CFI_LEGACY
 125 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
 126
 127 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 128 #define CONFIG_SYS_FLASH_SIZE           8 /* FLASH size is up to 8M */
 129
 130
 131 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 132 #define CONFIG_SYS_MAX_FLASH_SECT       135
 133
 134 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 135 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 136
 137 /*
 138  * FPGA
 139  */
 140 #define CONFIG_SYS_FPGA0_BASE           0xE0600000
 141 #define CONFIG_SYS_FPGA0_SIZE           1 /* FPGA size is 1M */
 142
 143
 144 #define CONFIG_SYS_FPGA_BASE(k)         CONFIG_SYS_FPGA0_BASE
 145 #define CONFIG_SYS_FPGA_DONE(k)         0x0010
 146
 147 #define CONFIG_SYS_FPGA_COUNT           1
 148
 149 #define CONFIG_SYS_MCLINK_MAX           3
 150
 151 #define CONFIG_SYS_FPGA_PTR \
 152         { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
 153
 154 #define CONFIG_SYS_FPGA_NO_RFL_HI
 155
 156 /*
 157  * Serial Port
 158  */
 159 #define CONFIG_SYS_NS16550_SERIAL
 160 #define CONFIG_SYS_NS16550_REG_SIZE     1
 161 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 162
 163 #define CONFIG_SYS_BAUDRATE_TABLE  \
 164         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 165
 166 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 167 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 168
 169 /* Pass open firmware flat tree */
 170
 171 /* I2C */
 172 #define CONFIG_SYS_I2C
 173 #define CONFIG_SYS_I2C_FSL
 174 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 175 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 176 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 177
 178 #define CONFIG_PCA953X                  /* NXP PCA9554 */
 179 #define CONFIG_SYS_I2C_PCA953X_WIDTH    { {0x24, 16}, {0x25, 16}, {0x26, 16}, \
 180                                           {0x3c, 8}, {0x3d, 8}, {0x3e, 8} }
 181
 182 #define CONFIG_PCA9698                  /* NXP PCA9698 */
 183
 184 #define CONFIG_SYS_I2C_IHS
 185 #define CONFIG_SYS_I2C_IHS_CH0
 186 #define CONFIG_SYS_I2C_IHS_SPEED_0              50000
 187 #define CONFIG_SYS_I2C_IHS_SLAVE_0              0x7F
 188 #define CONFIG_SYS_I2C_IHS_CH1
 189 #define CONFIG_SYS_I2C_IHS_SPEED_1              50000
 190 #define CONFIG_SYS_I2C_IHS_SLAVE_1              0x7F
 191 #define CONFIG_SYS_I2C_IHS_CH2
 192 #define CONFIG_SYS_I2C_IHS_SPEED_2              50000
 193 #define CONFIG_SYS_I2C_IHS_SLAVE_2              0x7F
 194 #define CONFIG_SYS_I2C_IHS_CH3
 195 #define CONFIG_SYS_I2C_IHS_SPEED_3              50000
 196 #define CONFIG_SYS_I2C_IHS_SLAVE_3              0x7F
 197
 198 #ifdef CONFIG_STRIDER_CON_DP
 199 #define CONFIG_SYS_I2C_IHS_DUAL
 200 #define CONFIG_SYS_I2C_IHS_CH0_1
 201 #define CONFIG_SYS_I2C_IHS_SPEED_0_1            50000
 202 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1            0x7F
 203 #define CONFIG_SYS_I2C_IHS_CH1_1
 204 #define CONFIG_SYS_I2C_IHS_SPEED_1_1            50000
 205 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1            0x7F
 206 #define CONFIG_SYS_I2C_IHS_CH2_1
 207 #define CONFIG_SYS_I2C_IHS_SPEED_2_1            50000
 208 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1            0x7F
 209 #define CONFIG_SYS_I2C_IHS_CH3_1
 210 #define CONFIG_SYS_I2C_IHS_SPEED_3_1            50000
 211 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1            0x7F
 212 #endif
 213
 214 /*
 215  * Software (bit-bang) I2C driver configuration
 216  */
 217 #define CONFIG_SYS_I2C_SOFT
 218 #define CONFIG_SOFT_I2C_READ_REPEATED_START
 219 #define CONFIG_SYS_I2C_SOFT_SPEED               50000
 220 #define CONFIG_SYS_I2C_SOFT_SLAVE               0x7F
 221 #define I2C_SOFT_DECLARATIONS2
 222 #define CONFIG_SYS_I2C_SOFT_SPEED_2             50000
 223 #define CONFIG_SYS_I2C_SOFT_SLAVE_2             0x7F
 224 #define I2C_SOFT_DECLARATIONS3
 225 #define CONFIG_SYS_I2C_SOFT_SPEED_3             50000
 226 #define CONFIG_SYS_I2C_SOFT_SLAVE_3             0x7F
 227 #define I2C_SOFT_DECLARATIONS4
 228 #define CONFIG_SYS_I2C_SOFT_SPEED_4             50000
 229 #define CONFIG_SYS_I2C_SOFT_SLAVE_4             0x7F
 230 #if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP)
 231 #define I2C_SOFT_DECLARATIONS5
 232 #define CONFIG_SYS_I2C_SOFT_SPEED_5             50000
 233 #define CONFIG_SYS_I2C_SOFT_SLAVE_5             0x7F
 234 #define I2C_SOFT_DECLARATIONS6
 235 #define CONFIG_SYS_I2C_SOFT_SPEED_6             50000
 236 #define CONFIG_SYS_I2C_SOFT_SLAVE_6             0x7F
 237 #define I2C_SOFT_DECLARATIONS7
 238 #define CONFIG_SYS_I2C_SOFT_SPEED_7             50000
 239 #define CONFIG_SYS_I2C_SOFT_SLAVE_7             0x7F
 240 #define I2C_SOFT_DECLARATIONS8
 241 #define CONFIG_SYS_I2C_SOFT_SPEED_8             50000
 242 #define CONFIG_SYS_I2C_SOFT_SLAVE_8             0x7F
 243 #endif
 244 #ifdef CONFIG_STRIDER_CON_DP
 245 #define I2C_SOFT_DECLARATIONS9
 246 #define CONFIG_SYS_I2C_SOFT_SPEED_9             50000
 247 #define CONFIG_SYS_I2C_SOFT_SLAVE_9             0x7F
 248 #define I2C_SOFT_DECLARATIONS10
 249 #define CONFIG_SYS_I2C_SOFT_SPEED_10            50000
 250 #define CONFIG_SYS_I2C_SOFT_SLAVE_10            0x7F
 251 #define I2C_SOFT_DECLARATIONS11
 252 #define CONFIG_SYS_I2C_SOFT_SPEED_11            50000
 253 #define CONFIG_SYS_I2C_SOFT_SLAVE_11            0x7F
 254 #define I2C_SOFT_DECLARATIONS12
 255 #define CONFIG_SYS_I2C_SOFT_SPEED_12            50000
 256 #define CONFIG_SYS_I2C_SOFT_SLAVE_12            0x7F
 257 #endif
 258
 259 #ifdef CONFIG_STRIDER_CON
 260 #define CONFIG_SYS_ICS8N3QV01_I2C               {5, 6, 7, 8}
 261 #define CONFIG_SYS_CH7301_I2C                   {5, 6, 7, 8}
 262 #define CONFIG_SYS_ADV7611_I2C                  {5, 6, 7, 8}
 263 #define CONFIG_SYS_DP501_I2C                    {1, 2, 3, 4}
 264 #define CONFIG_STRIDER_FANS                     { {10, 0x4c}, {11, 0x4c}, \
 265                                                   {12, 0x4c} }
 266 #elif defined(CONFIG_STRIDER_CON_DP)
 267 #define CONFIG_SYS_ICS8N3QV01_I2C               {13, 14, 15, 16, 17, 18, 19, 20}
 268 #define CONFIG_SYS_CH7301_I2C                   {1, 3, 5, 7}
 269 #define CONFIG_SYS_ADV7611_I2C                  {1, 3, 5, 7}
 270 #define CONFIG_SYS_DP501_I2C                    {1, 3, 5, 7, 2, 4, 6, 8}
 271 #define CONFIG_STRIDER_FANS                     { {10, 0x4c}, {11, 0x4c}, \
 272                                                   {12, 0x4c} }
 273 #elif defined(CONFIG_STRIDER_CPU_DP)
 274 #define CONFIG_SYS_CH7301_I2C                   {1, 2, 3, 4}
 275 #define CONFIG_SYS_ADV7611_I2C                  {1, 2, 3, 4}
 276 #define CONFIG_SYS_DP501_I2C                    {1, 2, 3, 4}
 277 #define CONFIG_STRIDER_FANS                     { {6, 0x4c}, {7, 0x4c}, \
 278                                                   {8, 0x4c} }
 279 #else
 280 #define CONFIG_SYS_CH7301_I2C                   {1, 2, 3, 4}
 281 #define CONFIG_SYS_ADV7611_I2C                  {1, 2, 3, 4}
 282 #define CONFIG_SYS_DP501_I2C                    {1, 2, 3, 4}
 283 #define CONFIG_STRIDER_FANS                     { {2, 0x18}, {3, 0x18}, \
 284                                                   {4, 0x18} }
 285 #endif
 286
 287 #ifndef __ASSEMBLY__
 288 void fpga_gpio_set(unsigned int bus, int pin);
 289 void fpga_gpio_clear(unsigned int bus, int pin);
 290 int fpga_gpio_get(unsigned int bus, int pin);
 291 void fpga_control_set(unsigned int bus, int pin);
 292 void fpga_control_clear(unsigned int bus, int pin);
 293 #endif
 294
 295 #ifdef CONFIG_STRIDER_CON
 296 #define I2C_SDA_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040)
 297 #define I2C_SCL_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
 298 #define I2C_FPGA_IDX    ((I2C_ADAP_HWNR > 3) ? \
 299                          (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR)
 300 #elif defined(CONFIG_STRIDER_CON_DP)
 301 #define I2C_SDA_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
 302 #define I2C_SCL_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
 303 #define I2C_FPGA_IDX    (I2C_ADAP_HWNR % 4)
 304 #else
 305 #define I2C_SDA_GPIO    0x0040
 306 #define I2C_SCL_GPIO    0x0020
 307 #define I2C_FPGA_IDX    I2C_ADAP_HWNR
 308 #endif
 309
 310 #ifdef CONFIG_STRIDER_CON_DP
 311 #define I2C_ACTIVE \
 312         do { \
 313                 if (I2C_ADAP_HWNR > 7) \
 314                         fpga_control_set(I2C_FPGA_IDX, 0x0004); \
 315                 else \
 316                         fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
 317         } while (0)
 318 #else
 319 #define I2C_ACTIVE      { }
 320 #endif
 321
 322 #define I2C_TRISTATE    { }
 323 #define I2C_READ \
 324         (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
 325 #define I2C_SDA(bit) \
 326         do { \
 327                 if (bit) \
 328                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 329                 else \
 330                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 331         } while (0)
 332 #define I2C_SCL(bit) \
 333         do { \
 334                 if (bit) \
 335                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 336                 else \
 337                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 338         } while (0)
 339 #define I2C_DELAY       udelay(25)      /* 1/4 I2C clock duration */
 340
 341 /*
 342  * Software (bit-bang) MII driver configuration
 343  */
 344 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 345 #define CONFIG_BITBANGMII_MULTI
 346
 347 /*
 348  * OSD Setup
 349  */
 350 #define CONFIG_SYS_OSD_SCREENS          1
 351 #define CONFIG_SYS_DP501_DIFFERENTIAL
 352 #define CONFIG_SYS_DP501_VCAPCTRL0      0x01 /* DDR mode 0, DE for H/VSYNC */
 353
 354 #ifdef CONFIG_STRIDER_CON_DP
 355 #define CONFIG_SYS_OSD_DH
 356 #endif
 357
 358 /*
 359  * General PCI
 360  * Addresses are mapped 1-1.
 361  */
 362 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 363 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 364 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 365 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 366 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 367 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 368 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 369 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 370 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 371
 372 /* enable PCIE clock */
 373 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
 374
 375 #define CONFIG_PCI_INDIRECT_BRIDGE
 376 #define CONFIG_PCIE
 377
 378 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 379 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
 380
 381 /*
 382  * TSEC
 383  */
 384 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 385 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 386
 387 /*
 388  * TSEC ethernet configuration
 389  */
 390 #define CONFIG_TSEC1
 391 #define CONFIG_TSEC1_NAME       "eTSEC0"
 392 #define TSEC1_PHY_ADDR          1
 393 #define TSEC1_PHYIDX            0
 394 #define TSEC1_FLAGS             0
 395
 396 /* Options are: eTSEC[0-1] */
 397 #define CONFIG_ETHPRIME         "eTSEC0"
 398
 399 /*
 400  * Environment
 401  */
 402 #if 1
 403 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 404                                  CONFIG_SYS_MONITOR_LEN)
 405 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 406 #define CONFIG_ENV_SIZE         0x2000
 407 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 408 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 409 #else
 410 #define CONFIG_ENV_SIZE         0x2000          /* 8KB */
 411 #endif
 412
 413 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 414 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 415
 416 /*
 417  * Command line configuration.
 418  */
 419
 420 /*
 421  * Miscellaneous configurable options
 422  */
 423 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 424 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 425
 426 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 427
 428 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 429
 430 /*
 431  * For booting Linux, the board info and command line data
 432  * have to be in the first 256 MB of memory, since this is
 433  * the maximum mapped by the Linux kernel during initialization.
 434  */
 435 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 436
 437 /*
 438  * Environment Configuration
 439  */
 440
 441 #define CONFIG_ENV_OVERWRITE
 442
 443 #if defined(CONFIG_TSEC_ENET)
 444 #define CONFIG_HAS_ETH0
 445 #endif
 446
 447 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 448
 449
 450 #define CONFIG_HOSTNAME         "hrcon"
 451 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 452 #define CONFIG_BOOTFILE         "uImage"
 453
 454 #define CONFIG_PREBOOT          /* enable preboot variable */
 455
 456 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 457         "netdev=eth0\0"                                                 \
 458         "consoledev=ttyS1\0"                                            \
 459         "u-boot=u-boot.bin\0"                                           \
 460         "kernel_addr=1000000\0"                                 \
 461         "fdt_addr=C00000\0"                                             \
 462         "fdtfile=hrcon.dtb\0"                           \
 463         "load=tftp ${loadaddr} ${u-boot}\0"                             \
 464         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 465                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
 466                 " +${filesize};cp.b ${fileaddr} "                       \
 467                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
 468         "upd=run load update\0"                                         \
 469
 470 #define CONFIG_NFSBOOTCOMMAND                                           \
 471         "setenv bootargs root=/dev/nfs rw "                             \
 472         "nfsroot=$serverip:$rootpath "                                  \
 473         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 474         "console=$consoledev,$baudrate $othbootargs;"                   \
 475         "tftp ${kernel_addr} $bootfile;"                                \
 476         "tftp ${fdt_addr} $fdtfile;"                                    \
 477         "bootm ${kernel_addr} - ${fdt_addr}"
 478
 479 #define CONFIG_MMCBOOTCOMMAND                                           \
 480         "setenv bootargs root=/dev/mmcblk0p3 rw rootwait "              \
 481         "console=$consoledev,$baudrate $othbootargs;"                   \
 482         "ext2load mmc 0:2 ${kernel_addr} $bootfile;"                    \
 483         "ext2load mmc 0:2 ${fdt_addr} $fdtfile;"                        \
 484         "bootm ${kernel_addr} - ${fdt_addr}"
 485
 486 #define CONFIG_BOOTCOMMAND              CONFIG_MMCBOOTCOMMAND
 487
 488 #endif  /* __CONFIG_H */