1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
12 * High Level Configuration Options
14 #define CONFIG_E300 1 /* E300 family */
16 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
21 #define CONFIG_FSL_SERDES
22 #define CONFIG_FSL_SERDES1 0xe3000
24 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
29 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
30 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
31 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
32 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
33 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
40 * Manually set up DDR parameters
41 * consist of one chip NT5TU64M16HG from NANYA
44 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
46 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
47 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
48 | CSCONFIG_ODT_RD_NEVER \
49 | CSCONFIG_ODT_WR_ONLY_CURRENT \
50 | CSCONFIG_BANK_BIT_3 \
51 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
53 #define CONFIG_SYS_DDR_TIMING_3 0
54 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
55 | (0 << TIMING_CFG0_WRT_SHIFT) \
56 | (0 << TIMING_CFG0_RRT_SHIFT) \
57 | (0 << TIMING_CFG0_WWT_SHIFT) \
58 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
59 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
60 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
61 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
63 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
64 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
65 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
66 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
67 | (9 << TIMING_CFG1_REFREC_SHIFT) \
68 | (2 << TIMING_CFG1_WRREC_SHIFT) \
69 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
70 | (2 << TIMING_CFG1_WRTORD_SHIFT))
72 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
73 | (4 << TIMING_CFG2_CPO_SHIFT) \
74 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
75 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
76 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
77 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
78 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
80 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
81 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
83 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
84 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
88 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
89 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
90 | (0x0242 << SDRAM_MODE_SD_SHIFT))
91 /* ODT 150ohm CL=4, AL=0 on SDRAM */
92 #define CONFIG_SYS_DDR_MODE2 0x00000000
97 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
98 #define CONFIG_SYS_MEMTEST_END 0x07f00000
101 * The reserved memory
103 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
105 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
106 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
109 * Initial RAM Base Address Setup
111 #define CONFIG_SYS_INIT_RAM_LOCK 1
112 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
113 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
114 #define CONFIG_SYS_GBL_DATA_OFFSET \
115 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
118 * Local Bus Configuration & Clock Setup
120 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
121 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
122 #define CONFIG_SYS_LBC_LBCR 0x00040000
125 * FLASH on the Local Bus
127 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
128 #define CONFIG_FLASH_CFI_LEGACY
129 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
131 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
132 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
135 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
136 #define CONFIG_SYS_MAX_FLASH_SECT 135
138 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
139 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
144 #define CONFIG_SYS_FPGA0_BASE 0xE0600000
145 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
148 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
149 #define CONFIG_SYS_FPGA_DONE(k) 0x0010
151 #define CONFIG_SYS_FPGA_COUNT 1
153 #define CONFIG_SYS_MCLINK_MAX 3
155 #define CONFIG_SYS_FPGA_PTR \
156 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
158 #define CONFIG_SYS_FPGA_NO_RFL_HI
163 #define CONFIG_SYS_NS16550_SERIAL
164 #define CONFIG_SYS_NS16550_REG_SIZE 1
165 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
167 #define CONFIG_SYS_BAUDRATE_TABLE \
168 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
170 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
171 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
173 /* Pass open firmware flat tree */
176 #define CONFIG_SYS_I2C
177 #define CONFIG_SYS_I2C_FSL
178 #define CONFIG_SYS_FSL_I2C_SPEED 400000
179 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
180 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
182 #define CONFIG_PCA953X /* NXP PCA9554 */
183 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \
184 {0x3c, 8}, {0x3d, 8}, {0x3e, 8} }
186 #define CONFIG_PCA9698 /* NXP PCA9698 */
188 #define CONFIG_SYS_I2C_IHS
189 #define CONFIG_SYS_I2C_IHS_CH0
190 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000
191 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
192 #define CONFIG_SYS_I2C_IHS_CH1
193 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000
194 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
195 #define CONFIG_SYS_I2C_IHS_CH2
196 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000
197 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
198 #define CONFIG_SYS_I2C_IHS_CH3
199 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000
200 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
202 #ifdef CONFIG_STRIDER_CON_DP
203 #define CONFIG_SYS_I2C_IHS_DUAL
204 #define CONFIG_SYS_I2C_IHS_CH0_1
205 #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
206 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
207 #define CONFIG_SYS_I2C_IHS_CH1_1
208 #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
209 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
210 #define CONFIG_SYS_I2C_IHS_CH2_1
211 #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000
212 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
213 #define CONFIG_SYS_I2C_IHS_CH3_1
214 #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000
215 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
219 * Software (bit-bang) I2C driver configuration
221 #define CONFIG_SYS_I2C_SOFT
222 #define CONFIG_SOFT_I2C_READ_REPEATED_START
223 #define CONFIG_SYS_I2C_SOFT_SPEED 50000
224 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
225 #define I2C_SOFT_DECLARATIONS2
226 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
227 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
228 #define I2C_SOFT_DECLARATIONS3
229 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
230 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
231 #define I2C_SOFT_DECLARATIONS4
232 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
233 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
234 #if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP)
235 #define I2C_SOFT_DECLARATIONS5
236 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
237 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
238 #define I2C_SOFT_DECLARATIONS6
239 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
240 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
241 #define I2C_SOFT_DECLARATIONS7
242 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
243 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
244 #define I2C_SOFT_DECLARATIONS8
245 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
246 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
248 #ifdef CONFIG_STRIDER_CON_DP
249 #define I2C_SOFT_DECLARATIONS9
250 #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000
251 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
252 #define I2C_SOFT_DECLARATIONS10
253 #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000
254 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
255 #define I2C_SOFT_DECLARATIONS11
256 #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000
257 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
258 #define I2C_SOFT_DECLARATIONS12
259 #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000
260 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
263 #ifdef CONFIG_STRIDER_CON
264 #define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
265 #define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
266 #define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8}
267 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
268 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
270 #elif defined(CONFIG_STRIDER_CON_DP)
271 #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20}
272 #define CONFIG_SYS_CH7301_I2C {1, 3, 5, 7}
273 #define CONFIG_SYS_ADV7611_I2C {1, 3, 5, 7}
274 #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8}
275 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
277 #elif defined(CONFIG_STRIDER_CPU_DP)
278 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
279 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
280 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
281 #define CONFIG_STRIDER_FANS { {6, 0x4c}, {7, 0x4c}, \
284 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
285 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
286 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
287 #define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \
292 void fpga_gpio_set(unsigned int bus, int pin);
293 void fpga_gpio_clear(unsigned int bus, int pin);
294 int fpga_gpio_get(unsigned int bus, int pin);
295 void fpga_control_set(unsigned int bus, int pin);
296 void fpga_control_clear(unsigned int bus, int pin);
299 #ifdef CONFIG_STRIDER_CON
300 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040)
301 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
302 #define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \
303 (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR)
304 #elif defined(CONFIG_STRIDER_CON_DP)
305 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
306 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
307 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4)
309 #define I2C_SDA_GPIO 0x0040
310 #define I2C_SCL_GPIO 0x0020
311 #define I2C_FPGA_IDX I2C_ADAP_HWNR
314 #ifdef CONFIG_STRIDER_CON_DP
317 if (I2C_ADAP_HWNR > 7) \
318 fpga_control_set(I2C_FPGA_IDX, 0x0004); \
320 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
323 #define I2C_ACTIVE { }
326 #define I2C_TRISTATE { }
328 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
329 #define I2C_SDA(bit) \
332 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
334 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
336 #define I2C_SCL(bit) \
339 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
341 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
343 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
346 * Software (bit-bang) MII driver configuration
348 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
349 #define CONFIG_BITBANGMII_MULTI
354 #define CONFIG_SYS_OSD_SCREENS 1
355 #define CONFIG_SYS_DP501_DIFFERENTIAL
356 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
358 #ifdef CONFIG_STRIDER_CON_DP
359 #define CONFIG_SYS_OSD_DH
364 * Addresses are mapped 1-1.
366 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
367 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
368 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
369 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
370 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
371 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
372 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
373 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
374 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
376 /* enable PCIE clock */
377 #define CONFIG_SYS_SCCR_PCIEXP1CM 1
379 #define CONFIG_PCI_INDIRECT_BRIDGE
382 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
383 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
388 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
389 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
392 * TSEC ethernet configuration
395 #define CONFIG_TSEC1_NAME "eTSEC0"
396 #define TSEC1_PHY_ADDR 1
397 #define TSEC1_PHYIDX 0
398 #define TSEC1_FLAGS 0
400 /* Options are: eTSEC[0-1] */
401 #define CONFIG_ETHPRIME "eTSEC0"
407 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
408 CONFIG_SYS_MONITOR_LEN)
409 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
410 #define CONFIG_ENV_SIZE 0x2000
411 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
412 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
414 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
417 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
418 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
421 * Command line configuration.
425 * Miscellaneous configurable options
427 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
428 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
430 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
432 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
435 * For booting Linux, the board info and command line data
436 * have to be in the first 256 MB of memory, since this is
437 * the maximum mapped by the Linux kernel during initialization.
439 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
442 * Environment Configuration
445 #define CONFIG_ENV_OVERWRITE
447 #if defined(CONFIG_TSEC_ENET)
448 #define CONFIG_HAS_ETH0
451 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
454 #define CONFIG_HOSTNAME "hrcon"
455 #define CONFIG_ROOTPATH "/opt/nfsroot"
456 #define CONFIG_BOOTFILE "uImage"
458 #define CONFIG_PREBOOT /* enable preboot variable */
460 #define CONFIG_EXTRA_ENV_SETTINGS \
462 "consoledev=ttyS1\0" \
463 "u-boot=u-boot.bin\0" \
464 "kernel_addr=1000000\0" \
465 "fdt_addr=C00000\0" \
466 "fdtfile=hrcon.dtb\0" \
467 "load=tftp ${loadaddr} ${u-boot}\0" \
468 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
469 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
470 " +${filesize};cp.b ${fileaddr} " \
471 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
472 "upd=run load update\0" \
474 #define CONFIG_NFSBOOTCOMMAND \
475 "setenv bootargs root=/dev/nfs rw " \
476 "nfsroot=$serverip:$rootpath " \
477 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
478 "console=$consoledev,$baudrate $othbootargs;" \
479 "tftp ${kernel_addr} $bootfile;" \
480 "tftp ${fdt_addr} $fdtfile;" \
481 "bootm ${kernel_addr} - ${fdt_addr}"
483 #define CONFIG_MMCBOOTCOMMAND \
484 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
485 "console=$consoledev,$baudrate $othbootargs;" \
486 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
487 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
488 "bootm ${kernel_addr} - ${fdt_addr}"
490 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
492 #endif /* __CONFIG_H */