include/configs/strider.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2014
   4  * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
   5  *
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  */
  14 #define CONFIG_E300             1 /* E300 family */
  15
  16 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
  17
  18 /*
  19  * SERDES
  20  */
  21 #define CONFIG_FSL_SERDES
  22 #define CONFIG_FSL_SERDES1      0xe3000
  23
  24 /*
  25  * DDR Setup
  26  */
  27 #define CONFIG_SYS_SDRAM_BASE           0x00000000 /* DDR is system memory */
  28 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  29 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  30                                 | DDRCDR_PZ_LOZ \
  31                                 | DDRCDR_NZ_LOZ \
  32                                 | DDRCDR_ODT \
  33                                 | DDRCDR_Q_DRN)
  34                                 /* 0x7b880001 */
  35 /*
  36  * Manually set up DDR parameters
  37  * consist of one chip NT5TU64M16HG from NANYA
  38  */
  39
  40 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
  41
  42 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
  43 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  44                                 | CSCONFIG_ODT_RD_NEVER \
  45                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
  46                                 | CSCONFIG_BANK_BIT_3 \
  47                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
  48                                 /* 0x80010102 */
  49 #define CONFIG_SYS_DDR_TIMING_3 0
  50 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  51                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  52                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  53                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  54                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  55                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  56                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  57                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  58                                 /* 0x00260802 */
  59 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  60                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  61                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  62                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
  63                                 | (9 << TIMING_CFG1_REFREC_SHIFT) \
  64                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
  65                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  66                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  67                                 /* 0x26279222 */
  68 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
  69                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
  70                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  71                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  72                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  73                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  74                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
  75                                 /* 0x021848c5 */
  76 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
  77                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  78                                 /* 0x08240100 */
  79 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
  80                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  81                                 | SDRAM_CFG_DBW_16)
  82                                 /* 0x43100000 */
  83
  84 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
  85 #define CONFIG_SYS_DDR_MODE             ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
  86                                 | (0x0242 << SDRAM_MODE_SD_SHIFT))
  87                                 /* ODT 150ohm CL=4, AL=0 on SDRAM */
  88 #define CONFIG_SYS_DDR_MODE2            0x00000000
  89
  90 /*
  91  * Memory test
  92  */
  93 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
  94 #define CONFIG_SYS_MEMTEST_END          0x07f00000
  95
  96 /*
  97  * The reserved memory
  98  */
  99 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 100
 101 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 102 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 103
 104 /*
 105  * Initial RAM Base Address Setup
 106  */
 107 #define CONFIG_SYS_INIT_RAM_LOCK        1
 108 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 109 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 110 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 111         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 112
 113 /*
 114  * Local Bus Configuration & Clock Setup
 115  */
 116 #define CONFIG_SYS_LBC_LBCR             0x00040000
 117
 118 /*
 119  * FLASH on the Local Bus
 120  */
 121 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 122 #define CONFIG_FLASH_CFI_LEGACY
 123 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
 124
 125 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 126 #define CONFIG_SYS_FLASH_SIZE           8 /* FLASH size is up to 8M */
 127
 128
 129 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 130 #define CONFIG_SYS_MAX_FLASH_SECT       135
 131
 132 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 133 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 134
 135 /*
 136  * FPGA
 137  */
 138 #define CONFIG_SYS_FPGA0_BASE           0xE0600000
 139 #define CONFIG_SYS_FPGA0_SIZE           1 /* FPGA size is 1M */
 140
 141
 142 #define CONFIG_SYS_FPGA_BASE(k)         CONFIG_SYS_FPGA0_BASE
 143 #define CONFIG_SYS_FPGA_DONE(k)         0x0010
 144
 145 #define CONFIG_SYS_FPGA_COUNT           1
 146
 147 #define CONFIG_SYS_MCLINK_MAX           3
 148
 149 #define CONFIG_SYS_FPGA_PTR \
 150         { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
 151
 152 #define CONFIG_SYS_FPGA_NO_RFL_HI
 153
 154 /*
 155  * Serial Port
 156  */
 157 #define CONFIG_SYS_NS16550_SERIAL
 158 #define CONFIG_SYS_NS16550_REG_SIZE     1
 159 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 160
 161 #define CONFIG_SYS_BAUDRATE_TABLE  \
 162         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 163
 164 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 165 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 166
 167 /* Pass open firmware flat tree */
 168
 169 /* I2C */
 170 #define CONFIG_SYS_I2C
 171 #define CONFIG_SYS_I2C_FSL
 172 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 173 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 174 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 175
 176 #define CONFIG_PCA953X                  /* NXP PCA9554 */
 177 #define CONFIG_SYS_I2C_PCA953X_WIDTH    { {0x24, 16}, {0x25, 16}, {0x26, 16}, \
 178                                           {0x3c, 8}, {0x3d, 8}, {0x3e, 8} }
 179
 180 #define CONFIG_PCA9698                  /* NXP PCA9698 */
 181
 182 #define CONFIG_SYS_I2C_IHS
 183 #define CONFIG_SYS_I2C_IHS_CH0
 184 #define CONFIG_SYS_I2C_IHS_SPEED_0              50000
 185 #define CONFIG_SYS_I2C_IHS_SLAVE_0              0x7F
 186 #define CONFIG_SYS_I2C_IHS_CH1
 187 #define CONFIG_SYS_I2C_IHS_SPEED_1              50000
 188 #define CONFIG_SYS_I2C_IHS_SLAVE_1              0x7F
 189 #define CONFIG_SYS_I2C_IHS_CH2
 190 #define CONFIG_SYS_I2C_IHS_SPEED_2              50000
 191 #define CONFIG_SYS_I2C_IHS_SLAVE_2              0x7F
 192 #define CONFIG_SYS_I2C_IHS_CH3
 193 #define CONFIG_SYS_I2C_IHS_SPEED_3              50000
 194 #define CONFIG_SYS_I2C_IHS_SLAVE_3              0x7F
 195
 196 #ifdef CONFIG_STRIDER_CON_DP
 197 #define CONFIG_SYS_I2C_IHS_DUAL
 198 #define CONFIG_SYS_I2C_IHS_CH0_1
 199 #define CONFIG_SYS_I2C_IHS_SPEED_0_1            50000
 200 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1            0x7F
 201 #define CONFIG_SYS_I2C_IHS_CH1_1
 202 #define CONFIG_SYS_I2C_IHS_SPEED_1_1            50000
 203 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1            0x7F
 204 #define CONFIG_SYS_I2C_IHS_CH2_1
 205 #define CONFIG_SYS_I2C_IHS_SPEED_2_1            50000
 206 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1            0x7F
 207 #define CONFIG_SYS_I2C_IHS_CH3_1
 208 #define CONFIG_SYS_I2C_IHS_SPEED_3_1            50000
 209 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1            0x7F
 210 #endif
 211
 212 /*
 213  * Software (bit-bang) I2C driver configuration
 214  */
 215 #define CONFIG_SYS_I2C_SOFT
 216 #define CONFIG_SOFT_I2C_READ_REPEATED_START
 217 #define CONFIG_SYS_I2C_SOFT_SPEED               50000
 218 #define CONFIG_SYS_I2C_SOFT_SLAVE               0x7F
 219 #define I2C_SOFT_DECLARATIONS2
 220 #define CONFIG_SYS_I2C_SOFT_SPEED_2             50000
 221 #define CONFIG_SYS_I2C_SOFT_SLAVE_2             0x7F
 222 #define I2C_SOFT_DECLARATIONS3
 223 #define CONFIG_SYS_I2C_SOFT_SPEED_3             50000
 224 #define CONFIG_SYS_I2C_SOFT_SLAVE_3             0x7F
 225 #define I2C_SOFT_DECLARATIONS4
 226 #define CONFIG_SYS_I2C_SOFT_SPEED_4             50000
 227 #define CONFIG_SYS_I2C_SOFT_SLAVE_4             0x7F
 228 #if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP)
 229 #define I2C_SOFT_DECLARATIONS5
 230 #define CONFIG_SYS_I2C_SOFT_SPEED_5             50000
 231 #define CONFIG_SYS_I2C_SOFT_SLAVE_5             0x7F
 232 #define I2C_SOFT_DECLARATIONS6
 233 #define CONFIG_SYS_I2C_SOFT_SPEED_6             50000
 234 #define CONFIG_SYS_I2C_SOFT_SLAVE_6             0x7F
 235 #define I2C_SOFT_DECLARATIONS7
 236 #define CONFIG_SYS_I2C_SOFT_SPEED_7             50000
 237 #define CONFIG_SYS_I2C_SOFT_SLAVE_7             0x7F
 238 #define I2C_SOFT_DECLARATIONS8
 239 #define CONFIG_SYS_I2C_SOFT_SPEED_8             50000
 240 #define CONFIG_SYS_I2C_SOFT_SLAVE_8             0x7F
 241 #endif
 242 #ifdef CONFIG_STRIDER_CON_DP
 243 #define I2C_SOFT_DECLARATIONS9
 244 #define CONFIG_SYS_I2C_SOFT_SPEED_9             50000
 245 #define CONFIG_SYS_I2C_SOFT_SLAVE_9             0x7F
 246 #define I2C_SOFT_DECLARATIONS10
 247 #define CONFIG_SYS_I2C_SOFT_SPEED_10            50000
 248 #define CONFIG_SYS_I2C_SOFT_SLAVE_10            0x7F
 249 #define I2C_SOFT_DECLARATIONS11
 250 #define CONFIG_SYS_I2C_SOFT_SPEED_11            50000
 251 #define CONFIG_SYS_I2C_SOFT_SLAVE_11            0x7F
 252 #define I2C_SOFT_DECLARATIONS12
 253 #define CONFIG_SYS_I2C_SOFT_SPEED_12            50000
 254 #define CONFIG_SYS_I2C_SOFT_SLAVE_12            0x7F
 255 #endif
 256
 257 #ifdef CONFIG_STRIDER_CON
 258 #define CONFIG_SYS_ICS8N3QV01_I2C               {5, 6, 7, 8}
 259 #define CONFIG_SYS_CH7301_I2C                   {5, 6, 7, 8}
 260 #define CONFIG_SYS_ADV7611_I2C                  {5, 6, 7, 8}
 261 #define CONFIG_SYS_DP501_I2C                    {1, 2, 3, 4}
 262 #define CONFIG_STRIDER_FANS                     { {10, 0x4c}, {11, 0x4c}, \
 263                                                   {12, 0x4c} }
 264 #elif defined(CONFIG_STRIDER_CON_DP)
 265 #define CONFIG_SYS_ICS8N3QV01_I2C               {13, 14, 15, 16, 17, 18, 19, 20}
 266 #define CONFIG_SYS_CH7301_I2C                   {1, 3, 5, 7}
 267 #define CONFIG_SYS_ADV7611_I2C                  {1, 3, 5, 7}
 268 #define CONFIG_SYS_DP501_I2C                    {1, 3, 5, 7, 2, 4, 6, 8}
 269 #define CONFIG_STRIDER_FANS                     { {10, 0x4c}, {11, 0x4c}, \
 270                                                   {12, 0x4c} }
 271 #elif defined(CONFIG_STRIDER_CPU_DP)
 272 #define CONFIG_SYS_CH7301_I2C                   {1, 2, 3, 4}
 273 #define CONFIG_SYS_ADV7611_I2C                  {1, 2, 3, 4}
 274 #define CONFIG_SYS_DP501_I2C                    {1, 2, 3, 4}
 275 #define CONFIG_STRIDER_FANS                     { {6, 0x4c}, {7, 0x4c}, \
 276                                                   {8, 0x4c} }
 277 #else
 278 #define CONFIG_SYS_CH7301_I2C                   {1, 2, 3, 4}
 279 #define CONFIG_SYS_ADV7611_I2C                  {1, 2, 3, 4}
 280 #define CONFIG_SYS_DP501_I2C                    {1, 2, 3, 4}
 281 #define CONFIG_STRIDER_FANS                     { {2, 0x18}, {3, 0x18}, \
 282                                                   {4, 0x18} }
 283 #endif
 284
 285 #ifndef __ASSEMBLY__
 286 void fpga_gpio_set(unsigned int bus, int pin);
 287 void fpga_gpio_clear(unsigned int bus, int pin);
 288 int fpga_gpio_get(unsigned int bus, int pin);
 289 void fpga_control_set(unsigned int bus, int pin);
 290 void fpga_control_clear(unsigned int bus, int pin);
 291 #endif
 292
 293 #ifdef CONFIG_STRIDER_CON
 294 #define I2C_SDA_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040)
 295 #define I2C_SCL_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
 296 #define I2C_FPGA_IDX    ((I2C_ADAP_HWNR > 3) ? \
 297                          (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR)
 298 #elif defined(CONFIG_STRIDER_CON_DP)
 299 #define I2C_SDA_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
 300 #define I2C_SCL_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
 301 #define I2C_FPGA_IDX    (I2C_ADAP_HWNR % 4)
 302 #else
 303 #define I2C_SDA_GPIO    0x0040
 304 #define I2C_SCL_GPIO    0x0020
 305 #define I2C_FPGA_IDX    I2C_ADAP_HWNR
 306 #endif
 307
 308 #ifdef CONFIG_STRIDER_CON_DP
 309 #define I2C_ACTIVE \
 310         do { \
 311                 if (I2C_ADAP_HWNR > 7) \
 312                         fpga_control_set(I2C_FPGA_IDX, 0x0004); \
 313                 else \
 314                         fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
 315         } while (0)
 316 #else
 317 #define I2C_ACTIVE      { }
 318 #endif
 319
 320 #define I2C_TRISTATE    { }
 321 #define I2C_READ \
 322         (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
 323 #define I2C_SDA(bit) \
 324         do { \
 325                 if (bit) \
 326                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 327                 else \
 328                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 329         } while (0)
 330 #define I2C_SCL(bit) \
 331         do { \
 332                 if (bit) \
 333                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 334                 else \
 335                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 336         } while (0)
 337 #define I2C_DELAY       udelay(25)      /* 1/4 I2C clock duration */
 338
 339 /*
 340  * Software (bit-bang) MII driver configuration
 341  */
 342 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 343 #define CONFIG_BITBANGMII_MULTI
 344
 345 /*
 346  * OSD Setup
 347  */
 348 #define CONFIG_SYS_OSD_SCREENS          1
 349 #define CONFIG_SYS_DP501_DIFFERENTIAL
 350 #define CONFIG_SYS_DP501_VCAPCTRL0      0x01 /* DDR mode 0, DE for H/VSYNC */
 351
 352 #ifdef CONFIG_STRIDER_CON_DP
 353 #define CONFIG_SYS_OSD_DH
 354 #endif
 355
 356 /*
 357  * General PCI
 358  * Addresses are mapped 1-1.
 359  */
 360 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 361 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 362 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 363 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 364 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 365 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 366 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 367 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 368 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 369
 370 /* enable PCIE clock */
 371 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
 372
 373 #define CONFIG_PCI_INDIRECT_BRIDGE
 374 #define CONFIG_PCIE
 375
 376 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 377 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
 378
 379 /*
 380  * TSEC
 381  */
 382 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 383 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 384
 385 /*
 386  * TSEC ethernet configuration
 387  */
 388 #define CONFIG_TSEC1
 389 #define CONFIG_TSEC1_NAME       "eTSEC0"
 390 #define TSEC1_PHY_ADDR          1
 391 #define TSEC1_PHYIDX            0
 392 #define TSEC1_FLAGS             0
 393
 394 /* Options are: eTSEC[0-1] */
 395 #define CONFIG_ETHPRIME         "eTSEC0"
 396
 397 /*
 398  * Environment
 399  */
 400 #if 1
 401 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 402                                  CONFIG_SYS_MONITOR_LEN)
 403 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 404 #define CONFIG_ENV_SIZE         0x2000
 405 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 406 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 407 #else
 408 #define CONFIG_ENV_SIZE         0x2000          /* 8KB */
 409 #endif
 410
 411 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 412 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 413
 414 /*
 415  * Command line configuration.
 416  */
 417
 418 /*
 419  * Miscellaneous configurable options
 420  */
 421 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 422 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 423
 424 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 425
 426 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 427
 428 /*
 429  * For booting Linux, the board info and command line data
 430  * have to be in the first 256 MB of memory, since this is
 431  * the maximum mapped by the Linux kernel during initialization.
 432  */
 433 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 434
 435 /*
 436  * Environment Configuration
 437  */
 438
 439 #define CONFIG_ENV_OVERWRITE
 440
 441 #if defined(CONFIG_TSEC_ENET)
 442 #define CONFIG_HAS_ETH0
 443 #endif
 444
 445 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 446
 447
 448 #define CONFIG_HOSTNAME         "hrcon"
 449 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 450 #define CONFIG_BOOTFILE         "uImage"
 451
 452 #define CONFIG_PREBOOT          /* enable preboot variable */
 453
 454 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 455         "netdev=eth0\0"                                                 \
 456         "consoledev=ttyS1\0"                                            \
 457         "u-boot=u-boot.bin\0"                                           \
 458         "kernel_addr=1000000\0"                                 \
 459         "fdt_addr=C00000\0"                                             \
 460         "fdtfile=hrcon.dtb\0"                           \
 461         "load=tftp ${loadaddr} ${u-boot}\0"                             \
 462         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 463                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
 464                 " +${filesize};cp.b ${fileaddr} "                       \
 465                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
 466         "upd=run load update\0"                                         \
 467
 468 #define CONFIG_NFSBOOTCOMMAND                                           \
 469         "setenv bootargs root=/dev/nfs rw "                             \
 470         "nfsroot=$serverip:$rootpath "                                  \
 471         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 472         "console=$consoledev,$baudrate $othbootargs;"                   \
 473         "tftp ${kernel_addr} $bootfile;"                                \
 474         "tftp ${fdt_addr} $fdtfile;"                                    \
 475         "bootm ${kernel_addr} - ${fdt_addr}"
 476
 477 #define CONFIG_MMCBOOTCOMMAND                                           \
 478         "setenv bootargs root=/dev/mmcblk0p3 rw rootwait "              \
 479         "console=$consoledev,$baudrate $othbootargs;"                   \
 480         "ext2load mmc 0:2 ${kernel_addr} $bootfile;"                    \
 481         "ext2load mmc 0:2 ${fdt_addr} $fdtfile;"                        \
 482         "bootm ${kernel_addr} - ${fdt_addr}"
 483
 484 #define CONFIG_BOOTCOMMAND              CONFIG_MMCBOOTCOMMAND
 485
 486 #endif  /* __CONFIG_H */