1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
12 * High Level Configuration Options
14 #define CONFIG_E300 1 /* E300 family */
16 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
21 #define CONFIG_FSL_SERDES
22 #define CONFIG_FSL_SERDES1 0xe3000
27 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
28 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
29 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
36 * Manually set up DDR parameters
37 * consist of one chip NT5TU64M16HG from NANYA
40 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
42 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
43 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
44 | CSCONFIG_ODT_RD_NEVER \
45 | CSCONFIG_ODT_WR_ONLY_CURRENT \
46 | CSCONFIG_BANK_BIT_3 \
47 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
49 #define CONFIG_SYS_DDR_TIMING_3 0
50 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
51 | (0 << TIMING_CFG0_WRT_SHIFT) \
52 | (0 << TIMING_CFG0_RRT_SHIFT) \
53 | (0 << TIMING_CFG0_WWT_SHIFT) \
54 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
55 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
56 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
57 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
59 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
60 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
61 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
62 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
63 | (9 << TIMING_CFG1_REFREC_SHIFT) \
64 | (2 << TIMING_CFG1_WRREC_SHIFT) \
65 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
66 | (2 << TIMING_CFG1_WRTORD_SHIFT))
68 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
69 | (4 << TIMING_CFG2_CPO_SHIFT) \
70 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
71 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
72 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
73 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
74 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
76 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
77 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
79 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
80 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
84 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
85 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
86 | (0x0242 << SDRAM_MODE_SD_SHIFT))
87 /* ODT 150ohm CL=4, AL=0 on SDRAM */
88 #define CONFIG_SYS_DDR_MODE2 0x00000000
97 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
99 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
100 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
103 * Initial RAM Base Address Setup
105 #define CONFIG_SYS_INIT_RAM_LOCK 1
106 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
107 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
108 #define CONFIG_SYS_GBL_DATA_OFFSET \
109 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
112 * FLASH on the Local Bus
114 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
115 #define CONFIG_FLASH_CFI_LEGACY
116 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
118 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
119 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
122 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
123 #define CONFIG_SYS_MAX_FLASH_SECT 135
125 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
126 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
128 #define CONFIG_SYS_FPGA_DONE(k) 0x0010
130 #define CONFIG_SYS_FPGA_COUNT 1
132 #define CONFIG_SYS_MCLINK_MAX 3
134 #define CONFIG_SYS_FPGA_PTR \
135 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
137 #define CONFIG_SYS_FPGA_NO_RFL_HI
142 #define CONFIG_SYS_NS16550_SERIAL
143 #define CONFIG_SYS_NS16550_REG_SIZE 1
144 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
146 #define CONFIG_SYS_BAUDRATE_TABLE \
147 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
149 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
150 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
152 /* Pass open firmware flat tree */
155 #define CONFIG_SYS_I2C
156 #define CONFIG_SYS_I2C_FSL
157 #define CONFIG_SYS_FSL_I2C_SPEED 400000
158 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
159 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
161 #define CONFIG_PCA953X /* NXP PCA9554 */
162 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \
163 {0x3c, 8}, {0x3d, 8}, {0x3e, 8} }
165 #define CONFIG_PCA9698 /* NXP PCA9698 */
167 #define CONFIG_SYS_I2C_IHS
168 #define CONFIG_SYS_I2C_IHS_CH0
169 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000
170 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
171 #define CONFIG_SYS_I2C_IHS_CH1
172 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000
173 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
174 #define CONFIG_SYS_I2C_IHS_CH2
175 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000
176 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
177 #define CONFIG_SYS_I2C_IHS_CH3
178 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000
179 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
181 #ifdef CONFIG_STRIDER_CON_DP
182 #define CONFIG_SYS_I2C_IHS_DUAL
183 #define CONFIG_SYS_I2C_IHS_CH0_1
184 #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
185 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
186 #define CONFIG_SYS_I2C_IHS_CH1_1
187 #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
188 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
189 #define CONFIG_SYS_I2C_IHS_CH2_1
190 #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000
191 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
192 #define CONFIG_SYS_I2C_IHS_CH3_1
193 #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000
194 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
198 * Software (bit-bang) I2C driver configuration
200 #define CONFIG_SYS_I2C_SOFT
201 #define CONFIG_SOFT_I2C_READ_REPEATED_START
202 #define CONFIG_SYS_I2C_SOFT_SPEED 50000
203 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
204 #define I2C_SOFT_DECLARATIONS2
205 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
206 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
207 #define I2C_SOFT_DECLARATIONS3
208 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
209 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
210 #define I2C_SOFT_DECLARATIONS4
211 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
212 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
213 #if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP)
214 #define I2C_SOFT_DECLARATIONS5
215 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
216 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
217 #define I2C_SOFT_DECLARATIONS6
218 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
219 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
220 #define I2C_SOFT_DECLARATIONS7
221 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
222 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
223 #define I2C_SOFT_DECLARATIONS8
224 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
225 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
227 #ifdef CONFIG_STRIDER_CON_DP
228 #define I2C_SOFT_DECLARATIONS9
229 #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000
230 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
231 #define I2C_SOFT_DECLARATIONS10
232 #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000
233 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
234 #define I2C_SOFT_DECLARATIONS11
235 #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000
236 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
237 #define I2C_SOFT_DECLARATIONS12
238 #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000
239 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
242 #ifdef CONFIG_STRIDER_CON
243 #define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
244 #define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
245 #define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8}
246 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
247 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
249 #elif defined(CONFIG_STRIDER_CON_DP)
250 #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20}
251 #define CONFIG_SYS_CH7301_I2C {1, 3, 5, 7}
252 #define CONFIG_SYS_ADV7611_I2C {1, 3, 5, 7}
253 #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8}
254 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
256 #elif defined(CONFIG_STRIDER_CPU_DP)
257 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
258 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
259 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
260 #define CONFIG_STRIDER_FANS { {6, 0x4c}, {7, 0x4c}, \
263 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
264 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
265 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
266 #define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \
271 void fpga_gpio_set(unsigned int bus, int pin);
272 void fpga_gpio_clear(unsigned int bus, int pin);
273 int fpga_gpio_get(unsigned int bus, int pin);
274 void fpga_control_set(unsigned int bus, int pin);
275 void fpga_control_clear(unsigned int bus, int pin);
278 #ifdef CONFIG_STRIDER_CON
279 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040)
280 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
281 #define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \
282 (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR)
283 #elif defined(CONFIG_STRIDER_CON_DP)
284 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
285 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
286 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4)
288 #define I2C_SDA_GPIO 0x0040
289 #define I2C_SCL_GPIO 0x0020
290 #define I2C_FPGA_IDX I2C_ADAP_HWNR
293 #ifdef CONFIG_STRIDER_CON_DP
296 if (I2C_ADAP_HWNR > 7) \
297 fpga_control_set(I2C_FPGA_IDX, 0x0004); \
299 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
302 #define I2C_ACTIVE { }
305 #define I2C_TRISTATE { }
307 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
308 #define I2C_SDA(bit) \
311 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
313 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
315 #define I2C_SCL(bit) \
318 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
320 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
322 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
325 * Software (bit-bang) MII driver configuration
327 #define CONFIG_BITBANGMII_MULTI
332 #define CONFIG_SYS_OSD_SCREENS 1
333 #define CONFIG_SYS_DP501_DIFFERENTIAL
334 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
336 #ifdef CONFIG_STRIDER_CON_DP
337 #define CONFIG_SYS_OSD_DH
342 * Addresses are mapped 1-1.
344 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
345 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
346 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
347 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
348 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
349 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
350 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
351 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
352 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
354 /* enable PCIE clock */
355 #define CONFIG_SYS_SCCR_PCIEXP1CM 1
357 #define CONFIG_PCI_INDIRECT_BRIDGE
360 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
361 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
366 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
367 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
370 * TSEC ethernet configuration
373 #define CONFIG_TSEC1_NAME "eTSEC0"
374 #define TSEC1_PHY_ADDR 1
375 #define TSEC1_PHYIDX 0
376 #define TSEC1_FLAGS 0
378 /* Options are: eTSEC[0-1] */
379 #define CONFIG_ETHPRIME "eTSEC0"
385 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
386 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
389 * Command line configuration.
393 * Miscellaneous configurable options
395 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
396 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
398 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
400 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
403 * For booting Linux, the board info and command line data
404 * have to be in the first 256 MB of memory, since this is
405 * the maximum mapped by the Linux kernel during initialization.
407 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
410 * Environment Configuration
413 #define CONFIG_ENV_OVERWRITE
415 #if defined(CONFIG_TSEC_ENET)
416 #define CONFIG_HAS_ETH0
419 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
422 #define CONFIG_HOSTNAME "hrcon"
423 #define CONFIG_ROOTPATH "/opt/nfsroot"
424 #define CONFIG_BOOTFILE "uImage"
426 #define CONFIG_EXTRA_ENV_SETTINGS \
428 "consoledev=ttyS1\0" \
429 "u-boot=u-boot.bin\0" \
430 "kernel_addr=1000000\0" \
431 "fdt_addr=C00000\0" \
432 "fdtfile=hrcon.dtb\0" \
433 "load=tftp ${loadaddr} ${u-boot}\0" \
434 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
435 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
436 " +${filesize};cp.b ${fileaddr} " \
437 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
438 "upd=run load update\0" \
440 #define CONFIG_NFSBOOTCOMMAND \
441 "setenv bootargs root=/dev/nfs rw " \
442 "nfsroot=$serverip:$rootpath " \
443 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
444 "console=$consoledev,$baudrate $othbootargs;" \
445 "tftp ${kernel_addr} $bootfile;" \
446 "tftp ${fdt_addr} $fdtfile;" \
447 "bootm ${kernel_addr} - ${fdt_addr}"
449 #define CONFIG_MMCBOOTCOMMAND \
450 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
451 "console=$consoledev,$baudrate $othbootargs;" \
452 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
453 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
454 "bootm ${kernel_addr} - ${fdt_addr}"
456 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
458 #endif /* __CONFIG_H */