2 * U-boot - stamp.h Configuration file for STAMP board
3 * having BF533 processor
5 * Copyright (c) 2005 blackfin.uclinux.org
7 * (C) Copyright 2000-2004
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #ifndef __CONFIG_STAMP_H__
30 #define __CONFIG_STAMP_H__
37 #define __ADSPLPBLACKFIN__ 1
38 #define __ADSPBF533__ 1
39 #define CONFIG_STAMP 1
40 #define CONFIG_RTC_BF533 1
42 /* FLASH/ETHERNET uses the same address range */
43 #define SHARED_RESOURCES 1
52 /* CONFIG_CLKIN_HZ is any value in Hz */
53 #define CONFIG_CLKIN_HZ 11059200
54 /* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
56 #define CONFIG_CLKIN_HALF 0
57 /* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
59 #define CONFIG_PLL_BYPASS 0
60 /* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
61 /* Values can range from 1-64 */
62 #define CONFIG_VCO_MULT 45
63 /* CONFIG_CCLK_DIV controls what the core clock divider is */
64 /* Values can be 1, 2, 4, or 8 ONLY */
65 #define CONFIG_CCLK_DIV 1
66 /* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
67 /* Values can range from 1-15 */
68 #define CONFIG_SCLK_DIV 6
74 #define CONFIG_IPADDR 192.168.0.15
75 #define CONFIG_NETMASK 255.255.255.0
76 #define CONFIG_GATEWAYIP 192.168.0.1
77 #define CONFIG_SERVERIP 192.168.0.2
78 #define CONFIG_HOSTNAME STAMP
79 #define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs
81 /* To remove hardcoding and enable MAC storage in EEPROM */
82 /* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
89 #define CFG_LONGHELP 1
91 #define CONFIG_BOOTDELAY 5
92 #define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
93 #define CONFIG_BOOTCOMMAND "run ramboot"
94 #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
96 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
103 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
105 #define CONFIG_EXTRA_ENV_SETTINGS \
106 "ramargs=setenv bootargs root=/dev/mtdblock0 rw\0" \
107 "nfsargs=setenv bootargs root=/dev/nfs rw " \
108 "nfsroot=$(serverip):$(rootpath)\0" \
109 "addip=setenv bootargs $(bootargs) " \
110 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
111 ":$(hostname):eth0:off\0" \
112 "ramboot=tftpboot 0x1000000 linux;" \
113 "run ramargs;run addip;bootelf\0" \
114 "nfsboot=tftpboot 0x1000000 linux;" \
115 "run nfsargs;run addip;bootelf\0" \
116 "flashboot=bootm 0x20100000\0" \
119 /* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
120 #include <cmd_confdefs.h>
127 #define CONFIG_BAUDRATE 57600
128 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
130 #define CFG_PROMPT "stamp>" /* Monitor Command Prompt */
131 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
132 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
134 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
136 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
137 #define CFG_MAXARGS 16 /* max number of command args */
138 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
140 #define CONFIG_LOADS_ECHO 1
147 #define CONFIG_DRIVER_SMC91111 1
148 #define CONFIG_SMC91111_BASE 0x20300300
149 /* To remove hardcoding and enable MAC storage in EEPROM */
150 /* #define HARDCODE_MAC 1 */
157 #define CFG_FLASH_CFI /* The flash is CFI compatible */
158 #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
159 #define CFG_FLASH_CFI_AMD_RESET
161 #define CFG_ENV_IS_IN_FLASH 1
163 #define CFG_FLASH_BASE 0x20000000
164 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
165 #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
167 #define CFG_ENV_ADDR 0x20020000
168 #define CFG_ENV_SIZE 0x10000
169 #define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
171 #define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */
172 #define CFG_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */
173 #define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
175 /* JFFS Partition offset set */
176 #define CFG_JFFS2_FIRST_BANK 0
177 #define CFG_JFFS2_NUM_BANKS 1
178 /* 512k reserved for u-boot */
179 #define CFG_JFFS2_FIRST_SECTOR 11
182 * following timeouts shall be used once the
183 * Flash real protection is enabled
185 #define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
186 #define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
190 * By default PF2 is used as SDA and PF3 as SCL on the Stamp board
192 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
194 * Software (bit-bang) I2C driver configuration
199 #define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;")
200 #define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
201 #define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
202 #define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
203 #define I2C_SDA(bit) if(bit) { \
204 *pFIO_FLAG_S = PF_SDA; \
208 *pFIO_FLAG_C = PF_SDA; \
211 #define I2C_SCL(bit) if(bit) { \
212 *pFIO_FLAG_S = PF_SCL; \
216 *pFIO_FLAG_C = PF_SCL; \
219 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
221 #define CFG_I2C_SPEED 50000
222 #define CFG_I2C_SLAVE 0xFE
225 * Compact Flash settings
228 /* Enabled below option for CF support */
229 /* #define CONFIG_STAMP_CF 1 */
231 #if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE)
233 #define CONFIG_MISC_INIT_R 1
234 #define CONFIG_DOS_PARTITION 1
239 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
240 #undef CONFIG_IDE_LED /* no led for ide supported */
241 #undef CONFIG_IDE_RESET /* no reset for ide supported */
243 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
244 #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
246 #define CFG_ATA_BASE_ADDR 0x20200000
247 #define CFG_ATA_IDE0_OFFSET 0x0000
249 #define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
250 #define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
251 #define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */
253 #define CFG_ATA_STRIDE 2
261 #define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */
262 #define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */
263 #define CONFIG_MEM_MT48LC64M4A2FB_7E 1
265 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
266 #define CFG_MEMTEST_END 0x07EFFFFF /* 1 ... 127 MB in DRAM */
267 #define CFG_LOAD_ADDR 0x01000000 /* default load address */
269 #define CFG_SDRAM_BASE 0x00000000
270 #define CFG_MAX_RAM_SIZE 0x08000000
272 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
273 #define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
275 #if ( CONFIG_CLKIN_HALF == 0 )
276 #define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
278 #define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
281 #if (CONFIG_PLL_BYPASS == 0)
282 #define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
283 #define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
285 #define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
286 #define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
290 * Miscellaneous configurable options
292 #define CFG_HZ 1000 /* 1ms time tick */
294 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
295 #define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
296 #define CFG_GBL_DATA_SIZE 0x4000
297 #define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
298 #define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
300 #define CFG_LARGE_IMAGE_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
302 #define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
307 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
310 * FLASH organization and environment definitions
312 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
314 /* 0xFF, 0xBBC3BBc3, 0x99B39983 */
315 /*#define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
316 #define AMBCTL0VAL (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \
317 B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN)
318 #define AMBCTL1VAL (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \
319 B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN)
321 #define AMGCTLVAL 0xFF
322 #define AMBCTL0VAL 0xBBC3BBC3
323 #define AMBCTL1VAL 0x99B39983
324 #define CF_AMBCTL1VAL 0x99B3ffc2
327 #define ET_EXEC_VDSP 0x8
328 #define SHT_STRTAB_VDSP 0x1
329 #define ELFSHDRSIZE_VDSP 0x2C
330 #define VDSP_ENTRY_ADDR 0xFFA00000