sunxi: Add support for using MII phy-s with the GMAC nic
[oweals/u-boot.git] / include / configs / spc1920.h
1 /*
2  * (C) Copyright 2006
3  * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de
4  *
5  * Configuation settings for the SPC1920 board.
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9
10 #ifndef __H
11 #define __CONFIG_H
12
13 #define CONFIG_SPC1920                  1       /* SPC1920 board */
14 #define CONFIG_MPC885                   1       /* MPC885 CPU */
15
16 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
17
18 #define CONFIG_8xx_CONS_SMC1            /* Console is on SMC1 */
19 #undef  CONFIG_8xx_CONS_SMC2
20 #undef  CONFIG_8xx_CONS_NONE
21
22 #define CONFIG_MII
23 #define CONFIG_MII_INIT         1
24 #undef CONFIG_ETHER_ON_FEC1
25 #define CONFIG_ETHER_ON_FEC2
26 #define FEC_ENET
27 #define CONFIG_FEC2_PHY         1
28
29 #define CONFIG_BAUDRATE         19200
30
31 /* use PLD CLK4 instead of brg */
32 #define CONFIG_SYS_SPC1920_SMC1_CLK4
33
34 #define CONFIG_8xx_OSCLK                10000000 /* 10 MHz oscillator on EXTCLK  */
35 #define CONFIG_8xx_CPUCLK_DEFAULT       50000000
36 #define CONFIG_SYS_8xx_CPUCLK_MIN               40000000
37 #define CONFIG_SYS_8xx_CPUCLK_MAX               133000000
38
39 #define CONFIG_SYS_RESET_ADDRESS                0xC0000000
40
41 #define CONFIG_BOARD_EARLY_INIT_F
42 #define CONFIG_LAST_STAGE_INIT
43
44 #if 0
45 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
46 #else
47 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
48 #endif
49
50 #define CONFIG_ENV_OVERWRITE
51
52 #define CONFIG_NFSBOOTCOMMAND                                                   \
53     "dhcp;"                                                                     \
54     "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath "                       \
55     "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;"              \
56     "bootm"
57
58 #define CONFIG_BOOTCOMMAND                                                      \
59     "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
60     "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;"              \
61     "bootm fe080000"
62
63 #undef CONFIG_BOOTARGS
64
65 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
66 #define CONFIG_BZIP2     /* include support for bzip2 compressed images */
67
68
69 /*
70  * BOOTP options
71  */
72 #define CONFIG_BOOTP_BOOTFILESIZE
73 #define CONFIG_BOOTP_BOOTPATH
74 #define CONFIG_BOOTP_GATEWAY
75 #define CONFIG_BOOTP_HOSTNAME
76
77
78 /*
79  * Command line configuration.
80  */
81 #include <config_cmd_default.h>
82
83 #define CONFIG_CMD_ASKENV
84 #define CONFIG_CMD_DATE
85 #define CONFIG_CMD_ECHO
86 #define CONFIG_CMD_IMMAP
87 #define CONFIG_CMD_JFFS2
88 #define CONFIG_CMD_NET
89 #define CONFIG_CMD_PING
90 #define CONFIG_CMD_DHCP
91 #define CONFIG_CMD_I2C
92 #define CONFIG_CMD_MII
93
94 /*
95  * Miscellaneous configurable options
96  */
97 #define CONFIG_SYS_LONGHELP                             /* undef to save memory         */
98 #define CONFIG_SYS_HUSH_PARSER
99
100 #if defined(CONFIG_CMD_KGDB)
101 #define CONFIG_SYS_CBSIZE               1024            /* Console I/O Buffer Size      */
102 #else
103 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
104 #endif
105
106 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size     */
107 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
108 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
109
110 #define CONFIG_SYS_LOAD_ADDR            0x00100000
111
112 #define CONFIG_SYS_BAUDRATE_TABLE       { 2400, 4800, 9600, 19200 }
113
114 /*
115  * Low Level Configuration Settings
116  * (address mappings, register initial values, etc.)
117  * You should know what you are doing if you make changes here.
118  */
119
120 /*-----------------------------------------------------------------------
121  * Internal Memory Mapped Register
122  */
123 #define CONFIG_SYS_IMMR         0xF0000000
124
125 /*-----------------------------------------------------------------------
126  * Definitions for initial stack pointer and data area (in DPRAM)
127  */
128 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
129 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
130 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
131 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
132
133 /*-----------------------------------------------------------------------
134  * Start addresses for the final memory configuration
135  * (Set up by the startup code)
136  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
137  */
138 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
139 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
140
141 /*
142  * For booting Linux, the board info and command line data
143  * have to be in the first 8 MB of memory, since this is
144  * the maximum mapped by the Linux kernel during initialization.
145  */
146 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
147
148 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
149 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 KB for monitor   */
150
151 #ifdef CONFIG_BZIP2
152 #define CONFIG_SYS_MALLOC_LEN           (2500 << 10)    /* Reserve ~2.5 MB for malloc() */
153 #else
154 #define CONFIG_SYS_MALLOC_LEN           (384 << 10)     /* Reserve 384 kB for malloc()  */
155 #endif /* CONFIG_BZIP2 */
156
157 #define CONFIG_SYS_ALLOC_DPRAM          1       /* use allocation routines      */
158
159 /*
160  * Flash
161  */
162 /*-----------------------------------------------------------------------
163  * Flash organisation
164  */
165 #define CONFIG_SYS_FLASH_BASE          0xFE000000
166 #define CONFIG_SYS_FLASH_CFI                           /* The flash is CFI compatible  */
167 #define CONFIG_FLASH_CFI_DRIVER                    /* Use common CFI driver        */
168 #define CONFIG_SYS_MAX_FLASH_BANKS     1               /* Max number of flash banks    */
169 #define CONFIG_SYS_MAX_FLASH_SECT      128             /* Max num of sects on one chip */
170
171 /* Environment is in flash */
172 #define CONFIG_ENV_IS_IN_FLASH
173 #define CONFIG_ENV_SECT_SIZE       0x40000         /* We use one complete sector   */
174 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
175
176 #define CONFIG_ENV_OVERWRITE
177
178 /*-----------------------------------------------------------------------
179  * Cache Configuration
180  */
181 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
182 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
183
184 #ifdef CONFIG_CMD_DATE
185 # define CONFIG_RTC_DS3231
186 # define CONFIG_SYS_I2C_RTC_ADDR      0x68
187 #endif
188
189 /*-----------------------------------------------------------------------
190  * I2C configuration
191  */
192 #if defined(CONFIG_CMD_I2C)
193 /* enable I2C and select the hardware/software driver */
194 #define CONFIG_SYS_I2C
195 #define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
196 #define CONFIG_SYS_I2C_SOFT_SPEED       93000   /* 93 kHz is supposed to work */
197 #define CONFIG_SYS_I2C_SOFT_SLAVE       0xFE
198 /*
199  * Software (bit-bang) I2C driver configuration
200  */
201 #define PB_SCL         0x00000020      /* PB 26 */
202 #define PB_SDA         0x00000010      /* PB 27 */
203
204 #define I2C_INIT       (immr->im_cpm.cp_pbdir |=  PB_SCL)
205 #define I2C_ACTIVE     (immr->im_cpm.cp_pbdir |=  PB_SDA)
206 #define I2C_TRISTATE   (immr->im_cpm.cp_pbdir &= ~PB_SDA)
207 #define I2C_READ       ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
208 #define I2C_SDA(bit)   if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
209                        else    immr->im_cpm.cp_pbdat &= ~PB_SDA
210 #define I2C_SCL(bit)   if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
211                        else    immr->im_cpm.cp_pbdat &= ~PB_SCL
212 #define I2C_DELAY      udelay(2)       /* 1/4 I2C clock duration */
213 #endif
214
215 /*-----------------------------------------------------------------------
216  * SYPCR - System Protection Control                            11-9
217  * SYPCR can only be written once after reset!
218  *-----------------------------------------------------------------------
219  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
220  */
221 #if defined(CONFIG_WATCHDOG)
222 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
223                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
224 #else
225 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
226 #endif
227
228 /*-----------------------------------------------------------------------
229  * SIUMCR - SIU Module Configuration                            11-6
230  *-----------------------------------------------------------------------
231  * PCMCIA config., multi-function pin tri-state
232  */
233 #define CONFIG_SYS_SIUMCR      (SIUMCR_FRC)
234
235 /*-----------------------------------------------------------------------
236  * TBSCR - Time Base Status and Control                         11-26
237  *-----------------------------------------------------------------------
238  * Clear Reference Interrupt Status, Timebase freezing enabled
239  */
240 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
241
242 /*-----------------------------------------------------------------------
243  * PISCR - Periodic Interrupt Status and Control                11-31
244  *-----------------------------------------------------------------------
245  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
246  */
247 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
248
249 /*-----------------------------------------------------------------------
250  * SCCR - System Clock and reset Control Register               15-27
251  *-----------------------------------------------------------------------
252  * Set clock output, timebase and RTC source and divider,
253  * power management and some other internal clocks
254  */
255 #define SCCR_MASK       SCCR_EBDF11
256 /* #define CONFIG_SYS_SCCR      SCCR_TBS */
257 #define CONFIG_SYS_SCCR (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
258                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
259                          SCCR_DFALCD00)
260
261 /*-----------------------------------------------------------------------
262  * DER - Debug Enable Register
263  *-----------------------------------------------------------------------
264  * Set to zero to prevent the processor from entering debug mode
265  */
266 #define CONFIG_SYS_DER           0
267
268
269 /* Because of the way the 860 starts up and assigns CS0 the entire
270  * address space, we have to set the memory controller differently.
271  * Normally, you write the option register first, and then enable the
272  * chip select by writing the base register.  For CS0, you must write
273  * the base register first, followed by the option register.
274  */
275
276
277 /*
278  * Init Memory Controller:
279  */
280
281 /* BR0 and OR0 (FLASH) */
282 #define FLASH_BASE0_PRELIM      CONFIG_SYS_FLASH_BASE   /* FLASH bank #0 */
283
284
285 /* used to re-map FLASH both when starting from SRAM or FLASH:
286  * restrict access enough to keep SRAM working (if any)
287  * but not too much to meddle with FLASH accesses
288  */
289 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
290 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
291
292 /*
293  * FLASH timing:
294  */
295 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
296                                  OR_SCY_6_CLK | OR_EHTR | OR_BI)
297
298 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
299 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
300 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
301
302
303 /*
304  * SDRAM CS1 UPMB
305  */
306 #define CONFIG_SYS_SDRAM_BASE   0x00000000
307 #define CONFIG_SYS_SDRAM_BASE_PRELIM CONFIG_SYS_SDRAM_BASE
308 #define SDRAM_MAX_SIZE  0x4000000 /* max 64 MB */
309
310 #define CONFIG_SYS_PRELIM_OR1_AM        0xF0000000
311 /* #define CONFIG_SYS_OR1_TIMING  OR_CSNT_SAM/\*  | OR_G5LS /\\* *\\/ *\/ */
312 #define SDRAM_TIMING    OR_SCY_0_CLK    /* SDRAM-Timing */
313
314 #define CONFIG_SYS_OR1_PRELIM   (CONFIG_SYS_PRELIM_OR1_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING)
315 #define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V)
316
317 /* #define CONFIG_SYS_OR1_FINAL   ((CONFIG_SYS_OR1_AM & OR_AM_MSK) | CONFIG_SYS_OR1_TIMING) */
318 /* #define CONFIG_SYS_BR1_FINAL   ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) */
319
320 #define CONFIG_SYS_PTB_PER_CLK  ((4096 * 16 * 1000) / (4 * 64))
321 #define CONFIG_SYS_PTA_PER_CLK 195
322 #define CONFIG_SYS_MBMR_PTB     195
323 #define CONFIG_SYS_MPTPR        MPTPR_PTP_DIV16
324 #define CONFIG_SYS_MAR          0x88
325
326 #define CONFIG_SYS_MBMR_8COL  ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
327                         MBMR_AMB_TYPE_0 | \
328                         MBMR_G0CLB_A10 | \
329                         MBMR_DSB_1_CYCL | \
330                         MBMR_RLFB_1X | \
331                         MBMR_WLFB_1X | \
332                         MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
333
334 #define CONFIG_SYS_MBMR_9COL  ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
335                         MBMR_AMB_TYPE_1 | \
336                         MBMR_G0CLB_A10 | \
337                         MBMR_DSB_1_CYCL | \
338                         MBMR_RLFB_1X | \
339                         MBMR_WLFB_1X | \
340                         MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
341
342
343 /*
344  * DSP Host Port Interface CS3
345  */
346 #define CONFIG_SYS_SPC1920_HPI_BASE   0x90000000
347 #define CONFIG_SYS_PRELIM_OR3_AM      0xF8000000
348
349 #define CONFIG_SYS_OR3         (CONFIG_SYS_PRELIM_OR3_AM | \
350                                        OR_G5LS | \
351                                        OR_SCY_0_CLK | \
352                                        OR_BI)
353
354 #define CONFIG_SYS_BR3 ((CONFIG_SYS_SPC1920_HPI_BASE & BR_BA_MSK) | \
355                                                BR_MS_UPMA | \
356                                                BR_PS_16 | \
357                                                BR_V)
358
359 #define CONFIG_SYS_MAMR (MAMR_GPL_A4DIS | \
360                 MAMR_RLFA_5X | \
361                 MAMR_WLFA_5X)
362
363 #define CONFIG_SPC1920_HPI_TEST
364
365 #ifdef CONFIG_SPC1920_HPI_TEST
366 #define HPI_REG(x)             (*((volatile u16 *) (CONFIG_SYS_SPC1920_HPI_BASE + x)))
367 #define HPI_HPIC_1             HPI_REG(0)
368 #define HPI_HPIC_2             HPI_REG(2)
369 #define HPI_HPIA_1             HPI_REG(0x2000008)
370 #define HPI_HPIA_2             HPI_REG(0x2000008 + 2)
371 #define HPI_HPID_INC_1         HPI_REG(0x1000004)
372 #define HPI_HPID_INC_2         HPI_REG(0x1000004 + 2)
373 #define HPI_HPID_NOINC_1       HPI_REG(0x300000c)
374 #define HPI_HPID_NOINC_2       HPI_REG(0x300000c + 2)
375 #endif /* CONFIG_SPC1920_HPI_TEST */
376
377 /*
378  * Ramtron FM18L08 FRAM 32KB on CS4
379  */
380 #define CONFIG_SYS_SPC1920_FRAM_BASE    0x80100000
381 #define CONFIG_SYS_PRELIM_OR4_AM        0xffff8000
382 #define CONFIG_SYS_OR4          (CONFIG_SYS_PRELIM_OR4_AM | \
383                                         OR_ACS_DIV2 | \
384                                         OR_BI | \
385                                         OR_SCY_4_CLK | \
386                                         OR_TRLX)
387
388 #define CONFIG_SYS_BR4 ((CONFIG_SYS_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
389
390 /*
391  * PLD CS5
392  */
393 #define CONFIG_SYS_SPC1920_PLD_BASE     0x80000000
394 #define CONFIG_SYS_PRELIM_OR5_AM        0xffff8000
395
396 #define CONFIG_SYS_OR5_PRELIM           (CONFIG_SYS_PRELIM_OR5_AM | \
397                                         OR_CSNT_SAM | \
398                                         OR_ACS_DIV1 | \
399                                         OR_BI | \
400                                         OR_SCY_0_CLK | \
401                                         OR_TRLX)
402
403 #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
404
405 #endif  /* __CONFIG_H */