ARM: configs: Add da850evm_nand to boot from NAND
[oweals/u-boot.git] / include / configs / socrates.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2008
4  * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
5  *
6  * Wolfgang Denk <wd@denx.de>
7  * Copyright 2004 Freescale Semiconductor.
8  * (C) Copyright 2002,2003 Motorola,Inc.
9  * Xianghua Xiao <X.Xiao@motorola.com>
10  */
11
12 /*
13  * Socrates
14  */
15
16 #ifndef __CONFIG_H
17 #define __CONFIG_H
18
19 /* High Level Configuration Options */
20 #define CONFIG_SOCRATES         1
21
22 #define CONFIG_PCI_INDIRECT_BRIDGE
23
24 /*
25  * Only possible on E500 Version 2 or newer cores.
26  */
27 #define CONFIG_ENABLE_36BIT_PHYS        1
28
29 /*
30  * sysclk for MPC85xx
31  *
32  * Two valid values are:
33  *    33000000
34  *    66000000
35  *
36  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
37  * is likely the desired value here, so that is now the default.
38  * The board, however, can run at 66MHz.  In any event, this value
39  * must match the settings of some switches.  Details can be found
40  * in the README.mpc85xxads.
41  */
42
43 #ifndef CONFIG_SYS_CLK_FREQ
44 #define CONFIG_SYS_CLK_FREQ     66666666
45 #endif
46
47 /*
48  * These can be toggled for performance analysis, otherwise use default.
49  */
50 #define CONFIG_L2_CACHE                 /* toggle L2 cache              */
51 #define CONFIG_BTB                      /* toggle branch predition      */
52
53 #define CONFIG_SYS_INIT_DBCR DBCR_IDM           /* Enable Debug Exceptions      */
54
55 #undef  CONFIG_SYS_DRAM_TEST                    /* memory test, takes time      */
56 #define CONFIG_SYS_MEMTEST_START        0x00400000
57 #define CONFIG_SYS_MEMTEST_END          0x00C00000
58
59 #define CONFIG_SYS_CCSRBAR              0xE0000000
60 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
61
62 /* DDR Setup */
63 #undef CONFIG_FSL_DDR_INTERACTIVE
64 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
65 #define CONFIG_DDR_SPD
66
67 #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER        /* DDR controller or DMA? */
68 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
69
70 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
71 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
72 #define CONFIG_VERY_BIG_RAM
73
74 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
75 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
76
77 /* I2C addresses of SPD EEPROMs */
78 #define SPD_EEPROM_ADDRESS      0x50    /* CTLR 0 DIMM 0 */
79
80 #define CONFIG_DDR_DEFAULT_CL   30              /* CAS latency 3        */
81
82 /* Hardcoded values, to use instead of SPD */
83 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000000f
84 #define CONFIG_SYS_DDR_CS0_CONFIG               0x80010102
85 #define CONFIG_SYS_DDR_TIMING_0         0x00260802
86 #define CONFIG_SYS_DDR_TIMING_1         0x3935D322
87 #define CONFIG_SYS_DDR_TIMING_2         0x14904CC8
88 #define CONFIG_SYS_DDR_MODE                     0x00480432
89 #define CONFIG_SYS_DDR_INTERVAL         0x030C0100
90 #define CONFIG_SYS_DDR_CONFIG_2         0x04400000
91 #define CONFIG_SYS_DDR_CONFIG                   0xC3008000
92 #define CONFIG_SYS_DDR_CLK_CONTROL              0x03800000
93 #define CONFIG_SYS_SDRAM_SIZE                   256 /* in Megs */
94
95 /*
96  * Flash on the LocalBus
97  */
98 #define CONFIG_SYS_LBC_CACHE_BASE       0xf0000000      /* Localbus cacheable    */
99
100 #define CONFIG_SYS_FLASH0               0xFE000000
101 #define CONFIG_SYS_FLASH1               0xFC000000
102 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
103
104 #define CONFIG_SYS_LBC_FLASH_BASE       CONFIG_SYS_FLASH1       /* Localbus flash start */
105 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH     */
106
107 #define CONFIG_SYS_BR0_PRELIM           0xfe001001      /* port size 16bit      */
108 #define CONFIG_SYS_OR0_PRELIM           0xfe000030      /* 32MB Flash           */
109 #define CONFIG_SYS_BR1_PRELIM           0xfc001001      /* port size 16bit      */
110 #define CONFIG_SYS_OR1_PRELIM           0xfe000030      /* 32MB Flash           */
111
112 #define CONFIG_SYS_FLASH_CFI                            /* flash is CFI compat. */
113 #define CONFIG_FLASH_CFI_DRIVER                 /* Use common CFI driver*/
114
115 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks      */
116 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* sectors per device   */
117 #undef  CONFIG_SYS_FLASH_CHECKSUM
118 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms)     */
119 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms)     */
120
121 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor     */
122
123 #define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg     */
124 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg          */
125 #define CONFIG_SYS_LBC_LSRT             0x20000000    /* LB sdram refresh timer */
126 #define CONFIG_SYS_LBC_MRTPR            0x20000000    /* LB refresh timer presc.*/
127
128 #define CONFIG_SYS_INIT_RAM_LOCK        1
129 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address  */
130 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size used area in RAM*/
131
132 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
133 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
134
135 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024)    /* Reserve 384KiB for Mon */
136 #define CONFIG_SYS_MALLOC_LEN           (4 << 20)       /* Reserve 4 MB for malloc */
137
138 /* FPGA and NAND */
139 #define CONFIG_SYS_FPGA_BASE            0xc0000000
140 #define CONFIG_SYS_FPGA_SIZE            0x00100000      /* 1 MB         */
141 #define CONFIG_SYS_HMI_BASE             0xc0010000
142 #define CONFIG_SYS_BR3_PRELIM           0xc0001881      /* UPMA, 32-bit */
143 #define CONFIG_SYS_OR3_PRELIM           0xfff00000      /* 1 MB         */
144
145 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_FPGA_BASE + 0x70)
146 #define CONFIG_SYS_MAX_NAND_DEVICE      1
147
148 /* LIME GDC */
149 #define CONFIG_SYS_LIME_BASE            0xc8000000
150 #define CONFIG_SYS_LIME_SIZE            0x04000000      /* 64 MB        */
151 #define CONFIG_SYS_BR2_PRELIM           0xc80018a1      /* UPMB, 32-bit */
152 #define CONFIG_SYS_OR2_PRELIM           0xfc000000      /* 64 MB        */
153
154 #define CONFIG_VIDEO_MB862xx
155 #define CONFIG_VIDEO_MB862xx_ACCEL
156 #define CONFIG_VIDEO_LOGO
157 #define CONFIG_VIDEO_BMP_LOGO
158 #define VIDEO_FB_16BPP_PIXEL_SWAP
159 #define VIDEO_FB_16BPP_WORD_SWAP
160 #define CONFIG_SPLASH_SCREEN
161 #define CONFIG_VIDEO_BMP_GZIP
162 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (2 << 20)       /* decompressed img */
163
164 /* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */
165 #define CONFIG_SYS_MB862xx_CCF          0x10000
166 /* SDRAM parameter */
167 #define CONFIG_SYS_MB862xx_MMR          0x4157BA63
168
169 /* Serial Port */
170
171 #define CONFIG_SYS_NS16550_SERIAL
172 #define CONFIG_SYS_NS16550_REG_SIZE     1
173 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
174
175 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
176 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
177
178 #define CONFIG_SYS_BAUDRATE_TABLE  \
179         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
180
181 /*
182  * I2C
183  */
184 #define CONFIG_SYS_I2C
185 #define CONFIG_SYS_I2C_FSL
186 #define CONFIG_SYS_FSL_I2C_SPEED        102124
187 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
188 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
189 #define CONFIG_SYS_FSL_I2C2_SPEED       102124
190 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
191 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
192
193 /* I2C RTC */
194 #define CONFIG_RTC_RX8025               /* Use Epson rx8025 rtc via i2c */
195 #define CONFIG_SYS_I2C_RTC_ADDR 0x32    /* at address 0x32              */
196
197 /* I2C W83782G HW-Monitoring IC */
198 #define CONFIG_SYS_I2C_W83782G_ADDR     0x28    /* W83782G address              */
199
200 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
201
202 /*
203  * General PCI
204  * Memory space is mapped 1-1.
205  */
206 #define CONFIG_SYS_PCI_PHYS             0x80000000      /* 1G PCI TLB */
207
208 /* PCI is clocked by the external source at 33 MHz */
209 #define CONFIG_PCI_CLK_FREQ     33000000
210 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
211 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
212 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M                 */
213 #define CONFIG_SYS_PCI1_IO_BASE 0xE2000000
214 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
215 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000      /* 16M                  */
216
217 #if defined(CONFIG_PCI)
218 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup  */
219 #endif  /* CONFIG_PCI */
220
221 #define CONFIG_TSEC1    1
222 #define CONFIG_TSEC1_NAME       "TSEC0"
223 #define CONFIG_TSEC3    1
224 #define CONFIG_TSEC3_NAME       "TSEC1"
225 #undef CONFIG_MPC85XX_FEC
226
227 #define TSEC1_PHY_ADDR          0
228 #define TSEC3_PHY_ADDR          1
229
230 #define TSEC1_PHYIDX            0
231 #define TSEC3_PHYIDX            0
232 #define TSEC1_FLAGS             TSEC_GIGABIT
233 #define TSEC3_FLAGS             TSEC_GIGABIT
234
235 /* Options are: TSEC[0,1] */
236 #define CONFIG_ETHPRIME         "TSEC0"
237
238 #define CONFIG_HAS_ETH0
239 #define CONFIG_HAS_ETH1
240
241 /*
242  * Environment
243  */
244 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env     */
245 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
246 #define CONFIG_ENV_SIZE         0x4000
247 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
248 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
249
250 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
251 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
252
253 #define CONFIG_TIMESTAMP                /* Print image info with ts     */
254
255 /*
256  * BOOTP options
257  */
258 #define CONFIG_BOOTP_BOOTFILESIZE
259
260 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
261
262 /*
263  * Miscellaneous configurable options
264  */
265 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address         */
266
267 /*
268  * For booting Linux, the board info and command line data
269  * have to be in the first 8 MB of memory, since this is
270  * the maximum mapped by the Linux kernel during initialization.
271  */
272 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux */
273
274 #if defined(CONFIG_CMD_KGDB)
275 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port*/
276 #endif
277
278 #define CONFIG_LOADADDR  200000         /* default addr for tftp & bootm*/
279
280
281 #define CONFIG_PREBOOT  "echo;" \
282         "echo Welcome on the ABB Socrates Board;" \
283         "echo"
284
285 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
286         "netdev=eth0\0"                                                 \
287         "consdev=ttyS0\0"                                               \
288         "uboot_file=/home/tftp/syscon3/u-boot.bin\0"                    \
289         "bootfile=/home/tftp/syscon3/uImage\0"                          \
290         "fdt_file=/home/tftp/syscon3/socrates.dtb\0"                    \
291         "initrd_file=/home/tftp/syscon3/uinitrd.gz\0"                   \
292         "uboot_addr=FFFA0000\0"                                         \
293         "kernel_addr=FE000000\0"                                        \
294         "fdt_addr=FE1E0000\0"                                           \
295         "ramdisk_addr=FE200000\0"                                       \
296         "fdt_addr_r=B00000\0"                                           \
297         "kernel_addr_r=200000\0"                                        \
298         "ramdisk_addr_r=400000\0"                                       \
299         "rootpath=/opt/eldk/ppc_85xxDP\0"                               \
300         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
301         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
302                 "nfsroot=$serverip:$rootpath\0"                         \
303         "addcons=setenv bootargs $bootargs "                            \
304                 "console=$consdev,$baudrate\0"                          \
305         "addip=setenv bootargs $bootargs "                              \
306                 "ip=$ipaddr:$serverip:$gatewayip:$netmask"              \
307                 ":$hostname:$netdev:off panic=1\0"                      \
308         "boot_nor=run ramargs addcons;"                                 \
309                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
310         "net_nfs=tftp ${kernel_addr_r} ${bootfile}; "                   \
311                 "tftp ${fdt_addr_r} ${fdt_file}; "                      \
312                 "run nfsargs addip addcons;"                            \
313                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
314         "update_uboot=tftp 100000 ${uboot_file};"                       \
315                 "protect off fffa0000 ffffffff;"                        \
316                 "era fffa0000 ffffffff;"                                \
317                 "cp.b 100000 fffa0000 ${filesize};"                     \
318                 "setenv filesize;saveenv\0"                             \
319         "update_kernel=tftp 100000 ${bootfile};"                        \
320                 "era fe000000 fe1dffff;"                                \
321                 "cp.b 100000 fe000000 ${filesize};"                     \
322                 "setenv filesize;saveenv\0"                             \
323         "update_fdt=tftp 100000 ${fdt_file};"                           \
324                 "era fe1e0000 fe1fffff;"                                \
325                 "cp.b 100000 fe1e0000 ${filesize};"                     \
326                 "setenv filesize;saveenv\0"                             \
327         "update_initrd=tftp 100000 ${initrd_file};"                     \
328                 "era fe200000 fe9fffff;"                                \
329                 "cp.b 100000 fe200000 ${filesize};"                     \
330                 "setenv filesize;saveenv\0"                             \
331         "clean_data=era fea00000 fff5ffff\0"                            \
332         "usbargs=setenv bootargs root=/dev/sda1 rw\0"                   \
333         "load_usb=usb start;"                                           \
334                 "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0"      \
335         "boot_usb=run load_usb usbargs addcons;"                        \
336                 "bootm ${kernel_addr_r} - ${fdt_addr};"                 \
337                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
338         ""
339 #define CONFIG_BOOTCOMMAND      "run boot_nor"
340
341 /* pass open firmware flat tree */
342
343 /* USB support */
344 #define CONFIG_USB_OHCI_NEW             1
345 #define CONFIG_PCI_OHCI                 1
346 #define CONFIG_PCI_OHCI_DEVNO           3 /* Number in PCI list */
347 #define CONFIG_PCI_EHCI_DEVNO           (CONFIG_PCI_OHCI_DEVNO / 2)
348 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
349 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "ohci_pci"
350 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
351
352 #endif  /* __CONFIG_H */