3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
5 * Wolfgang Denk <wd@denx.de>
6 * Copyright 2004 Freescale Semiconductor.
7 * (C) Copyright 2002,2003 Motorola,Inc.
8 * Xianghua Xiao <X.Xiao@motorola.com>
10 * SPDX-License-Identifier: GPL-2.0+
20 /* High Level Configuration Options */
21 #define CONFIG_BOOKE 1 /* BOOKE */
22 #define CONFIG_E500 1 /* BOOKE e500 family */
23 #define CONFIG_MPC8544 1
24 #define CONFIG_SOCRATES 1
25 #define CONFIG_DISPLAY_BOARDINFO
27 #define CONFIG_SYS_TEXT_BASE 0xfff80000
30 #define CONFIG_PCI_INDIRECT_BRIDGE
32 #define CONFIG_TSEC_ENET /* tsec ethernet support */
34 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
35 #define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
37 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
40 * Only possible on E500 Version 2 or newer cores.
42 #define CONFIG_ENABLE_36BIT_PHYS 1
47 * Two valid values are:
51 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
52 * is likely the desired value here, so that is now the default.
53 * The board, however, can run at 66MHz. In any event, this value
54 * must match the settings of some switches. Details can be found
55 * in the README.mpc85xxads.
58 #ifndef CONFIG_SYS_CLK_FREQ
59 #define CONFIG_SYS_CLK_FREQ 66666666
63 * These can be toggled for performance analysis, otherwise use default.
65 #define CONFIG_L2_CACHE /* toggle L2 cache */
66 #define CONFIG_BTB /* toggle branch predition */
68 #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
70 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
71 #define CONFIG_SYS_MEMTEST_START 0x00400000
72 #define CONFIG_SYS_MEMTEST_END 0x00C00000
74 #define CONFIG_SYS_CCSRBAR 0xE0000000
75 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
78 #define CONFIG_SYS_FSL_DDR2
79 #undef CONFIG_FSL_DDR_INTERACTIVE
80 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
81 #define CONFIG_DDR_SPD
83 #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
84 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
86 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
87 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
88 #define CONFIG_VERY_BIG_RAM
90 #define CONFIG_NUM_DDR_CONTROLLERS 1
91 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
92 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
94 /* I2C addresses of SPD EEPROMs */
95 #define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */
97 #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
99 /* Hardcoded values, to use instead of SPD */
100 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
101 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
102 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
103 #define CONFIG_SYS_DDR_TIMING_1 0x3935D322
104 #define CONFIG_SYS_DDR_TIMING_2 0x14904CC8
105 #define CONFIG_SYS_DDR_MODE 0x00480432
106 #define CONFIG_SYS_DDR_INTERVAL 0x030C0100
107 #define CONFIG_SYS_DDR_CONFIG_2 0x04400000
108 #define CONFIG_SYS_DDR_CONFIG 0xC3008000
109 #define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000
110 #define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */
113 * Flash on the LocalBus
115 #define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
117 #define CONFIG_SYS_FLASH0 0xFE000000
118 #define CONFIG_SYS_FLASH1 0xFC000000
119 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
121 #define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */
122 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */
124 #define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */
125 #define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */
126 #define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */
127 #define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */
129 #define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */
130 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/
132 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
133 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
134 #undef CONFIG_SYS_FLASH_CHECKSUM
135 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
136 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
138 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
140 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
141 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
142 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
143 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
145 #define CONFIG_SYS_INIT_RAM_LOCK 1
146 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
147 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/
149 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
150 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
152 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */
153 #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */
156 #define CONFIG_SYS_FPGA_BASE 0xc0000000
157 #define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
158 #define CONFIG_SYS_HMI_BASE 0xc0010000
159 #define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */
160 #define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */
162 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
163 #define CONFIG_SYS_MAX_NAND_DEVICE 1
164 #define CONFIG_CMD_NAND
167 #define CONFIG_SYS_LIME_BASE 0xc8000000
168 #define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */
169 #define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */
170 #define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */
173 #define CONFIG_VIDEO_MB862xx
174 #define CONFIG_VIDEO_MB862xx_ACCEL
175 #define CONFIG_CFB_CONSOLE
176 #define CONFIG_VIDEO_LOGO
177 #define CONFIG_VIDEO_BMP_LOGO
178 #define CONFIG_CONSOLE_EXTRA_INFO
179 #define VIDEO_FB_16BPP_PIXEL_SWAP
180 #define VIDEO_FB_16BPP_WORD_SWAP
181 #define CONFIG_VGA_AS_SINGLE_DEVICE
182 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
183 #define CONFIG_VIDEO_SW_CURSOR
184 #define CONFIG_SPLASH_SCREEN
185 #define CONFIG_VIDEO_BMP_GZIP
186 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
188 /* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */
189 #define CONFIG_SYS_MB862xx_CCF 0x10000
190 /* SDRAM parameter */
191 #define CONFIG_SYS_MB862xx_MMR 0x4157BA63
195 #define CONFIG_CONS_INDEX 1
196 #define CONFIG_SYS_NS16550_SERIAL
197 #define CONFIG_SYS_NS16550_REG_SIZE 1
198 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
200 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
201 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
203 #define CONFIG_BAUDRATE 115200
205 #define CONFIG_SYS_BAUDRATE_TABLE \
206 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
208 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
209 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
214 #define CONFIG_SYS_I2C
215 #define CONFIG_SYS_I2C_FSL
216 #define CONFIG_SYS_FSL_I2C_SPEED 102124
217 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
218 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
219 #define CONFIG_SYS_FSL_I2C2_SPEED 102124
220 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
221 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
224 #define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */
225 #define CONFIG_SYS_I2C_RTC_ADDR 0x32 /* at address 0x32 */
227 /* I2C W83782G HW-Monitoring IC */
228 #define CONFIG_SYS_I2C_W83782G_ADDR 0x28 /* W83782G address */
230 /* I2C temp sensor */
231 /* Socrates uses Maxim's DS75, which is compatible with LM75 */
232 #define CONFIG_DTT_LM75 1
233 #define CONFIG_DTT_SENSORS {4} /* Sensor addresses */
234 #define CONFIG_SYS_DTT_MAX_TEMP 125
235 #define CONFIG_SYS_DTT_LOW_TEMP -55
236 #define CONFIG_SYS_DTT_HYSTERESIS 3
237 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
241 * Memory space is mapped 1-1.
243 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
245 /* PCI is clocked by the external source at 33 MHz */
246 #define CONFIG_PCI_CLK_FREQ 33000000
247 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
248 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
249 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
250 #define CONFIG_SYS_PCI1_IO_BASE 0xE2000000
251 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
252 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
254 #if defined(CONFIG_PCI)
255 #define CONFIG_PCI_PNP /* do pci plug-and-play */
256 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
257 #endif /* CONFIG_PCI */
259 #define CONFIG_MII 1 /* MII PHY management */
260 #define CONFIG_TSEC1 1
261 #define CONFIG_TSEC1_NAME "TSEC0"
262 #define CONFIG_TSEC3 1
263 #define CONFIG_TSEC3_NAME "TSEC1"
264 #undef CONFIG_MPC85XX_FEC
266 #define TSEC1_PHY_ADDR 0
267 #define TSEC3_PHY_ADDR 1
269 #define TSEC1_PHYIDX 0
270 #define TSEC3_PHYIDX 0
271 #define TSEC1_FLAGS TSEC_GIGABIT
272 #define TSEC3_FLAGS TSEC_GIGABIT
274 /* Options are: TSEC[0,1] */
275 #define CONFIG_ETHPRIME "TSEC0"
276 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
278 #define CONFIG_HAS_ETH0
279 #define CONFIG_HAS_ETH1
284 #define CONFIG_ENV_IS_IN_FLASH 1
285 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
286 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
287 #define CONFIG_ENV_SIZE 0x4000
288 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
289 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
291 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
292 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
294 #define CONFIG_TIMESTAMP /* Print image info with ts */
299 #define CONFIG_BOOTP_BOOTFILESIZE
300 #define CONFIG_BOOTP_BOOTPATH
301 #define CONFIG_BOOTP_GATEWAY
302 #define CONFIG_BOOTP_HOSTNAME
305 * Command line configuration.
307 #define CONFIG_CMD_BMP
308 #define CONFIG_CMD_DATE
309 #define CONFIG_CMD_DTT
310 #undef CONFIG_CMD_EEPROM
311 #define CONFIG_CMD_EXT2 /* EXT2 Support */
312 #define CONFIG_CMD_SDRAM
313 #define CONFIG_CMD_MII
314 #define CONFIG_CMD_REGINFO
316 #if defined(CONFIG_PCI)
317 #define CONFIG_CMD_PCI
320 #undef CONFIG_WATCHDOG /* watchdog disabled */
323 * Miscellaneous configurable options
325 #define CONFIG_SYS_LONGHELP /* undef to save memory */
326 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
328 #if defined(CONFIG_CMD_KGDB)
329 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
331 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
334 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buf Size */
335 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
336 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
339 * For booting Linux, the board info and command line data
340 * have to be in the first 8 MB of memory, since this is
341 * the maximum mapped by the Linux kernel during initialization.
343 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
345 #if defined(CONFIG_CMD_KGDB)
346 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
349 #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
351 #define CONFIG_BOOTDELAY 1 /* -1 disables auto-boot */
353 #define CONFIG_PREBOOT "echo;" \
354 "echo Welcome on the ABB Socrates Board;" \
357 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
359 #define CONFIG_EXTRA_ENV_SETTINGS \
362 "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \
363 "bootfile=/home/tftp/syscon3/uImage\0" \
364 "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \
365 "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \
366 "uboot_addr=FFFA0000\0" \
367 "kernel_addr=FE000000\0" \
368 "fdt_addr=FE1E0000\0" \
369 "ramdisk_addr=FE200000\0" \
370 "fdt_addr_r=B00000\0" \
371 "kernel_addr_r=200000\0" \
372 "ramdisk_addr_r=400000\0" \
373 "rootpath=/opt/eldk/ppc_85xxDP\0" \
374 "ramargs=setenv bootargs root=/dev/ram rw\0" \
375 "nfsargs=setenv bootargs root=/dev/nfs rw " \
376 "nfsroot=$serverip:$rootpath\0" \
377 "addcons=setenv bootargs $bootargs " \
378 "console=$consdev,$baudrate\0" \
379 "addip=setenv bootargs $bootargs " \
380 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
381 ":$hostname:$netdev:off panic=1\0" \
382 "boot_nor=run ramargs addcons;" \
383 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
384 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
385 "tftp ${fdt_addr_r} ${fdt_file}; " \
386 "run nfsargs addip addcons;" \
387 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
388 "update_uboot=tftp 100000 ${uboot_file};" \
389 "protect off fffa0000 ffffffff;" \
390 "era fffa0000 ffffffff;" \
391 "cp.b 100000 fffa0000 ${filesize};" \
392 "setenv filesize;saveenv\0" \
393 "update_kernel=tftp 100000 ${bootfile};" \
394 "era fe000000 fe1dffff;" \
395 "cp.b 100000 fe000000 ${filesize};" \
396 "setenv filesize;saveenv\0" \
397 "update_fdt=tftp 100000 ${fdt_file};" \
398 "era fe1e0000 fe1fffff;" \
399 "cp.b 100000 fe1e0000 ${filesize};" \
400 "setenv filesize;saveenv\0" \
401 "update_initrd=tftp 100000 ${initrd_file};" \
402 "era fe200000 fe9fffff;" \
403 "cp.b 100000 fe200000 ${filesize};" \
404 "setenv filesize;saveenv\0" \
405 "clean_data=era fea00000 fff5ffff\0" \
406 "usbargs=setenv bootargs root=/dev/sda1 rw\0" \
407 "load_usb=usb start;" \
408 "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \
409 "boot_usb=run load_usb usbargs addcons;" \
410 "bootm ${kernel_addr_r} - ${fdt_addr};" \
411 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
413 #define CONFIG_BOOTCOMMAND "run boot_nor"
415 /* pass open firmware flat tree */
418 #define CONFIG_USB_OHCI_NEW 1
419 #define CONFIG_PCI_OHCI 1
420 #define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */
421 #define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2)
422 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
423 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
424 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
425 #define CONFIG_DOS_PARTITION 1
426 #define CONFIG_USB_STORAGE 1
428 #endif /* __CONFIG_H */