sunxi: Add support for using MII phy-s with the GMAC nic
[oweals/u-boot.git] / include / configs / socrates.h
1 /*
2  * (C) Copyright 2008
3  * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
4  *
5  * Wolfgang Denk <wd@denx.de>
6  * Copyright 2004 Freescale Semiconductor.
7  * (C) Copyright 2002,2003 Motorola,Inc.
8  * Xianghua Xiao <X.Xiao@motorola.com>
9  *
10  * SPDX-License-Identifier:     GPL-2.0+
11  */
12
13 /*
14  * Socrates
15  */
16
17 #ifndef __CONFIG_H
18 #define __CONFIG_H
19
20 /* new uImage format support */
21 #define CONFIG_FIT              1
22 #define CONFIG_OF_LIBFDT        1
23 #define CONFIG_FIT_VERBOSE      1 /* enable fit_format_{error,warning}() */
24
25 /* High Level Configuration Options */
26 #define CONFIG_BOOKE            1       /* BOOKE                        */
27 #define CONFIG_E500             1       /* BOOKE e500 family            */
28 #define CONFIG_MPC8544          1
29 #define CONFIG_SOCRATES         1
30
31 #define CONFIG_SYS_TEXT_BASE    0xfff80000
32
33 #define CONFIG_PCI
34 #define CONFIG_PCI_INDIRECT_BRIDGE
35
36 #define CONFIG_TSEC_ENET                /* tsec ethernet support        */
37
38 #define CONFIG_MISC_INIT_R      1       /* Call misc_init_r             */
39 #define CONFIG_BOARD_EARLY_INIT_R 1     /* Call board_early_init_r      */
40
41 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
42
43 /*
44  * Only possible on E500 Version 2 or newer cores.
45  */
46 #define CONFIG_ENABLE_36BIT_PHYS        1
47
48 /*
49  * sysclk for MPC85xx
50  *
51  * Two valid values are:
52  *    33000000
53  *    66000000
54  *
55  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
56  * is likely the desired value here, so that is now the default.
57  * The board, however, can run at 66MHz.  In any event, this value
58  * must match the settings of some switches.  Details can be found
59  * in the README.mpc85xxads.
60  */
61
62 #ifndef CONFIG_SYS_CLK_FREQ
63 #define CONFIG_SYS_CLK_FREQ     66666666
64 #endif
65
66 /*
67  * These can be toggled for performance analysis, otherwise use default.
68  */
69 #define CONFIG_L2_CACHE                 /* toggle L2 cache              */
70 #define CONFIG_BTB                      /* toggle branch predition      */
71
72 #define CONFIG_SYS_INIT_DBCR DBCR_IDM           /* Enable Debug Exceptions      */
73
74 #undef  CONFIG_SYS_DRAM_TEST                    /* memory test, takes time      */
75 #define CONFIG_SYS_MEMTEST_START        0x00400000
76 #define CONFIG_SYS_MEMTEST_END          0x00C00000
77
78 #define CONFIG_SYS_CCSRBAR              0xE0000000
79 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
80
81 /* DDR Setup */
82 #define CONFIG_SYS_FSL_DDR2
83 #undef CONFIG_FSL_DDR_INTERACTIVE
84 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
85 #define CONFIG_DDR_SPD
86
87 #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER        /* DDR controller or DMA? */
88 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
89
90 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
91 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
92 #define CONFIG_VERY_BIG_RAM
93
94 #define CONFIG_NUM_DDR_CONTROLLERS      1
95 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
96 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
97
98 /* I2C addresses of SPD EEPROMs */
99 #define SPD_EEPROM_ADDRESS      0x50    /* CTLR 0 DIMM 0 */
100
101 #define CONFIG_DDR_DEFAULT_CL   30              /* CAS latency 3        */
102
103 /* Hardcoded values, to use instead of SPD */
104 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000000f
105 #define CONFIG_SYS_DDR_CS0_CONFIG               0x80010102
106 #define CONFIG_SYS_DDR_TIMING_0         0x00260802
107 #define CONFIG_SYS_DDR_TIMING_1         0x3935D322
108 #define CONFIG_SYS_DDR_TIMING_2         0x14904CC8
109 #define CONFIG_SYS_DDR_MODE                     0x00480432
110 #define CONFIG_SYS_DDR_INTERVAL         0x030C0100
111 #define CONFIG_SYS_DDR_CONFIG_2         0x04400000
112 #define CONFIG_SYS_DDR_CONFIG                   0xC3008000
113 #define CONFIG_SYS_DDR_CLK_CONTROL              0x03800000
114 #define CONFIG_SYS_SDRAM_SIZE                   256 /* in Megs */
115
116 /*
117  * Flash on the LocalBus
118  */
119 #define CONFIG_SYS_LBC_CACHE_BASE       0xf0000000      /* Localbus cacheable    */
120
121 #define CONFIG_SYS_FLASH0               0xFE000000
122 #define CONFIG_SYS_FLASH1               0xFC000000
123 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
124
125 #define CONFIG_SYS_LBC_FLASH_BASE       CONFIG_SYS_FLASH1       /* Localbus flash start */
126 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH     */
127
128 #define CONFIG_SYS_BR0_PRELIM           0xfe001001      /* port size 16bit      */
129 #define CONFIG_SYS_OR0_PRELIM           0xfe000030      /* 32MB Flash           */
130 #define CONFIG_SYS_BR1_PRELIM           0xfc001001      /* port size 16bit      */
131 #define CONFIG_SYS_OR1_PRELIM           0xfe000030      /* 32MB Flash           */
132
133 #define CONFIG_SYS_FLASH_CFI                            /* flash is CFI compat. */
134 #define CONFIG_FLASH_CFI_DRIVER                 /* Use common CFI driver*/
135
136 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks      */
137 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* sectors per device   */
138 #undef  CONFIG_SYS_FLASH_CHECKSUM
139 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms)     */
140 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms)     */
141
142 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor     */
143
144 #define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg     */
145 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg          */
146 #define CONFIG_SYS_LBC_LSRT             0x20000000    /* LB sdram refresh timer */
147 #define CONFIG_SYS_LBC_MRTPR            0x20000000    /* LB refresh timer presc.*/
148
149 #define CONFIG_SYS_INIT_RAM_LOCK        1
150 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address  */
151 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size used area in RAM*/
152
153 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
154 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
155
156 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024)    /* Reserve 384KiB for Mon */
157 #define CONFIG_SYS_MALLOC_LEN           (4 << 20)       /* Reserve 4 MB for malloc */
158
159 /* FPGA and NAND */
160 #define CONFIG_SYS_FPGA_BASE            0xc0000000
161 #define CONFIG_SYS_FPGA_SIZE            0x00100000      /* 1 MB         */
162 #define CONFIG_SYS_HMI_BASE             0xc0010000
163 #define CONFIG_SYS_BR3_PRELIM           0xc0001881      /* UPMA, 32-bit */
164 #define CONFIG_SYS_OR3_PRELIM           0xfff00000      /* 1 MB         */
165
166 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_FPGA_BASE + 0x70)
167 #define CONFIG_SYS_MAX_NAND_DEVICE      1
168 #define CONFIG_CMD_NAND
169
170 /* LIME GDC */
171 #define CONFIG_SYS_LIME_BASE            0xc8000000
172 #define CONFIG_SYS_LIME_SIZE            0x04000000      /* 64 MB        */
173 #define CONFIG_SYS_BR2_PRELIM           0xc80018a1      /* UPMB, 32-bit */
174 #define CONFIG_SYS_OR2_PRELIM           0xfc000000      /* 64 MB        */
175
176 #define CONFIG_VIDEO
177 #define CONFIG_VIDEO_MB862xx
178 #define CONFIG_VIDEO_MB862xx_ACCEL
179 #define CONFIG_CFB_CONSOLE
180 #define CONFIG_VIDEO_LOGO
181 #define CONFIG_VIDEO_BMP_LOGO
182 #define CONFIG_CONSOLE_EXTRA_INFO
183 #define VIDEO_FB_16BPP_PIXEL_SWAP
184 #define VIDEO_FB_16BPP_WORD_SWAP
185 #define CONFIG_VGA_AS_SINGLE_DEVICE
186 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
187 #define CONFIG_VIDEO_SW_CURSOR
188 #define CONFIG_SPLASH_SCREEN
189 #define CONFIG_VIDEO_BMP_GZIP
190 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (2 << 20)       /* decompressed img */
191
192 /* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */
193 #define CONFIG_SYS_MB862xx_CCF          0x10000
194 /* SDRAM parameter */
195 #define CONFIG_SYS_MB862xx_MMR          0x4157BA63
196
197 /* Serial Port */
198
199 #define CONFIG_CONS_INDEX     1
200 #define CONFIG_SYS_NS16550
201 #define CONFIG_SYS_NS16550_SERIAL
202 #define CONFIG_SYS_NS16550_REG_SIZE     1
203 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
204
205 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
206 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
207
208 #define CONFIG_BAUDRATE         115200
209
210 #define CONFIG_SYS_BAUDRATE_TABLE  \
211         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
212
213 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
214 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support */
215 #define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser          */
216
217
218 /*
219  * I2C
220  */
221 #define CONFIG_SYS_I2C
222 #define CONFIG_SYS_I2C_FSL
223 #define CONFIG_SYS_FSL_I2C_SPEED        102124
224 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
225 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
226 #define CONFIG_SYS_FSL_I2C2_SPEED       102124
227 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
228 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
229
230 /* I2C RTC */
231 #define CONFIG_RTC_RX8025               /* Use Epson rx8025 rtc via i2c */
232 #define CONFIG_SYS_I2C_RTC_ADDR 0x32    /* at address 0x32              */
233
234 /* I2C W83782G HW-Monitoring IC */
235 #define CONFIG_SYS_I2C_W83782G_ADDR     0x28    /* W83782G address              */
236
237 /* I2C temp sensor */
238 /* Socrates uses Maxim's        DS75, which is compatible with LM75 */
239 #define CONFIG_DTT_LM75         1
240 #define CONFIG_DTT_SENSORS      {4}             /* Sensor addresses     */
241 #define CONFIG_SYS_DTT_MAX_TEMP 125
242 #define CONFIG_SYS_DTT_LOW_TEMP -55
243 #define CONFIG_SYS_DTT_HYSTERESIS       3
244 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
245
246 /*
247  * General PCI
248  * Memory space is mapped 1-1.
249  */
250 #define CONFIG_SYS_PCI_PHYS             0x80000000      /* 1G PCI TLB */
251
252 /* PCI is clocked by the external source at 33 MHz */
253 #define CONFIG_PCI_CLK_FREQ     33000000
254 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
255 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
256 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M                 */
257 #define CONFIG_SYS_PCI1_IO_BASE 0xE2000000
258 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
259 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000      /* 16M                  */
260
261 #if defined(CONFIG_PCI)
262 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
263 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup  */
264 #endif  /* CONFIG_PCI */
265
266
267 #define CONFIG_MII              1       /* MII PHY management */
268 #define CONFIG_TSEC1    1
269 #define CONFIG_TSEC1_NAME       "TSEC0"
270 #define CONFIG_TSEC3    1
271 #define CONFIG_TSEC3_NAME       "TSEC1"
272 #undef CONFIG_MPC85XX_FEC
273
274 #define TSEC1_PHY_ADDR          0
275 #define TSEC3_PHY_ADDR          1
276
277 #define TSEC1_PHYIDX            0
278 #define TSEC3_PHYIDX            0
279 #define TSEC1_FLAGS             TSEC_GIGABIT
280 #define TSEC3_FLAGS             TSEC_GIGABIT
281
282 /* Options are: TSEC[0,1] */
283 #define CONFIG_ETHPRIME         "TSEC0"
284 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
285
286 #define CONFIG_HAS_ETH0
287 #define CONFIG_HAS_ETH1
288
289 /*
290  * Environment
291  */
292 #define CONFIG_ENV_IS_IN_FLASH  1
293 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env     */
294 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
295 #define CONFIG_ENV_SIZE         0x4000
296 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
297 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
298
299 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
300 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
301
302 #define CONFIG_TIMESTAMP                /* Print image info with ts     */
303
304
305 /*
306  * BOOTP options
307  */
308 #define CONFIG_BOOTP_BOOTFILESIZE
309 #define CONFIG_BOOTP_BOOTPATH
310 #define CONFIG_BOOTP_GATEWAY
311 #define CONFIG_BOOTP_HOSTNAME
312
313
314 /*
315  * Command line configuration.
316  */
317 #include <config_cmd_default.h>
318
319 #define CONFIG_CMD_BMP
320 #define CONFIG_CMD_DATE
321 #define CONFIG_CMD_DHCP
322 #define CONFIG_CMD_DTT
323 #undef CONFIG_CMD_EEPROM
324 #define CONFIG_CMD_EXT2         /* EXT2 Support                 */
325 #define CONFIG_CMD_I2C
326 #define CONFIG_CMD_SDRAM
327 #define CONFIG_CMD_MII
328 #undef CONFIG_CMD_NFS
329 #define CONFIG_CMD_PING
330 #define CONFIG_CMD_SNTP
331 #define CONFIG_CMD_USB
332 #define CONFIG_CMD_REGINFO
333
334 #if defined(CONFIG_PCI)
335     #define CONFIG_CMD_PCI
336 #endif
337
338 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
339
340 /*
341  * Miscellaneous configurable options
342  */
343 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
344 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address         */
345
346 #if defined(CONFIG_CMD_KGDB)
347     #define CONFIG_SYS_CBSIZE   1024            /* Console I/O Buffer Size      */
348 #else
349     #define CONFIG_SYS_CBSIZE   256             /* Console I/O Buffer Size      */
350 #endif
351
352 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buf Size    */
353 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
354 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
355
356 /*
357  * For booting Linux, the board info and command line data
358  * have to be in the first 8 MB of memory, since this is
359  * the maximum mapped by the Linux kernel during initialization.
360  */
361 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux */
362
363 #if defined(CONFIG_CMD_KGDB)
364 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port*/
365 #endif
366
367
368 #define CONFIG_LOADADDR  200000         /* default addr for tftp & bootm*/
369
370 #define CONFIG_BOOTDELAY 1              /* -1 disables auto-boot        */
371
372 #define CONFIG_PREBOOT  "echo;" \
373         "echo Welcome on the ABB Socrates Board;" \
374         "echo"
375
376 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs   */
377
378 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
379         "netdev=eth0\0"                                                 \
380         "consdev=ttyS0\0"                                               \
381         "uboot_file=/home/tftp/syscon3/u-boot.bin\0"                    \
382         "bootfile=/home/tftp/syscon3/uImage\0"                          \
383         "fdt_file=/home/tftp/syscon3/socrates.dtb\0"                    \
384         "initrd_file=/home/tftp/syscon3/uinitrd.gz\0"                   \
385         "uboot_addr=FFFA0000\0"                                         \
386         "kernel_addr=FE000000\0"                                        \
387         "fdt_addr=FE1E0000\0"                                           \
388         "ramdisk_addr=FE200000\0"                                       \
389         "fdt_addr_r=B00000\0"                                           \
390         "kernel_addr_r=200000\0"                                        \
391         "ramdisk_addr_r=400000\0"                                       \
392         "rootpath=/opt/eldk/ppc_85xxDP\0"                               \
393         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
394         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
395                 "nfsroot=$serverip:$rootpath\0"                         \
396         "addcons=setenv bootargs $bootargs "                            \
397                 "console=$consdev,$baudrate\0"                          \
398         "addip=setenv bootargs $bootargs "                              \
399                 "ip=$ipaddr:$serverip:$gatewayip:$netmask"              \
400                 ":$hostname:$netdev:off panic=1\0"                      \
401         "boot_nor=run ramargs addcons;"                                 \
402                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
403         "net_nfs=tftp ${kernel_addr_r} ${bootfile}; "                   \
404                 "tftp ${fdt_addr_r} ${fdt_file}; "                      \
405                 "run nfsargs addip addcons;"                            \
406                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
407         "update_uboot=tftp 100000 ${uboot_file};"                       \
408                 "protect off fffa0000 ffffffff;"                        \
409                 "era fffa0000 ffffffff;"                                \
410                 "cp.b 100000 fffa0000 ${filesize};"                     \
411                 "setenv filesize;saveenv\0"                             \
412         "update_kernel=tftp 100000 ${bootfile};"                        \
413                 "era fe000000 fe1dffff;"                                \
414                 "cp.b 100000 fe000000 ${filesize};"                     \
415                 "setenv filesize;saveenv\0"                             \
416         "update_fdt=tftp 100000 ${fdt_file};"                           \
417                 "era fe1e0000 fe1fffff;"                                \
418                 "cp.b 100000 fe1e0000 ${filesize};"                     \
419                 "setenv filesize;saveenv\0"                             \
420         "update_initrd=tftp 100000 ${initrd_file};"                     \
421                 "era fe200000 fe9fffff;"                                \
422                 "cp.b 100000 fe200000 ${filesize};"                     \
423                 "setenv filesize;saveenv\0"                             \
424         "clean_data=era fea00000 fff5ffff\0"                            \
425         "usbargs=setenv bootargs root=/dev/sda1 rw\0"                   \
426         "load_usb=usb start;"                                           \
427                 "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0"      \
428         "boot_usb=run load_usb usbargs addcons;"                        \
429                 "bootm ${kernel_addr_r} - ${fdt_addr};"                 \
430                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
431         ""
432 #define CONFIG_BOOTCOMMAND      "run boot_nor"
433
434 /* pass open firmware flat tree */
435 #define CONFIG_OF_LIBFDT        1
436 #define CONFIG_OF_BOARD_SETUP   1
437
438 /* USB support */
439 #define CONFIG_USB_OHCI_NEW             1
440 #define CONFIG_PCI_OHCI                 1
441 #define CONFIG_PCI_OHCI_DEVNO           3 /* Number in PCI list */
442 #define CONFIG_PCI_EHCI_DEVNO           (CONFIG_PCI_OHCI_DEVNO / 2)
443 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
444 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "ohci_pci"
445 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
446 #define CONFIG_DOS_PARTITION            1
447 #define CONFIG_USB_STORAGE              1
448
449 #endif  /* __CONFIG_H */