ARM: configs: Add da850evm_nand to boot from NAND
[oweals/u-boot.git] / include / configs / socfpga_stratix10_socdk.h
1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
4  *
5  */
6
7 #ifndef __CONFIG_SOCFGPA_STRATIX10_H__
8 #define __CONFIG_SOCFGPA_STRATIX10_H__
9
10 #include <asm/arch/base_addr_s10.h>
11 #include <asm/arch/handoff_s10.h>
12
13 /*
14  * U-Boot general configurations
15  */
16 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
17 #define CONFIG_LOADADDR                 0x2000000
18 #define CONFIG_SYS_LOAD_ADDR            CONFIG_LOADADDR
19 #define CONFIG_REMAKE_ELF
20 /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
21 #define CPU_RELEASE_ADDR                0xFFD12210
22 #define CONFIG_SYS_CACHELINE_SIZE       64
23 #define CONFIG_SYS_MEM_RESERVE_SECURE   0       /* using OCRAM, not DDR */
24
25 /*
26  * U-Boot console configurations
27  */
28 #define CONFIG_SYS_MAXARGS              64
29 #define CONFIG_SYS_CBSIZE               2048
30 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
31                                         sizeof(CONFIG_SYS_PROMPT) + 16)
32 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
33
34 /* Extend size of kernel image for uncompression */
35 #define CONFIG_SYS_BOOTM_LEN            (32 * 1024 * 1024)
36
37 /*
38  * U-Boot run time memory configurations
39  */
40 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFE00000
41 #define CONFIG_SYS_INIT_RAM_SIZE        0x40000
42 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR  \
43                                         + CONFIG_SYS_INIT_RAM_SIZE \
44                                         - S10_HANDOFF_SIZE)
45 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_SP_ADDR)
46 #define CONFIG_SYS_MALLOC_LEN           (5 * 1024 * 1024)
47
48 /*
49  * U-Boot environment configurations
50  */
51 #define CONFIG_ENV_SIZE                 0x1000
52 #define CONFIG_SYS_MMC_ENV_DEV          0       /* device 0 */
53 #define CONFIG_ENV_OFFSET               512     /* just after the MBR */
54
55 /*
56  * QSPI support
57  */
58  #ifdef CONFIG_CADENCE_QSPI
59 /* Enable it if you want to use dual-stacked mode */
60 #undef CONFIG_SF_DUAL_FLASH
61 /*#define CONFIG_QSPI_RBF_ADDR          0x720000*/
62
63 /* Flash device info */
64 #define CONFIG_SF_DEFAULT_SPEED         (50000000)
65 #define CONFIG_SF_DEFAULT_MODE          (SPI_MODE_3 | SPI_RX_QUAD)
66 #define CONFIG_SF_DEFAULT_BUS           0
67 #define CONFIG_SF_DEFAULT_CS            0
68
69 /*#define CONFIG_ENV_IS_IN_SPI_FLASH*/
70 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
71 #undef CONFIG_ENV_OFFSET
72 #undef CONFIG_ENV_SIZE
73 #define CONFIG_ENV_OFFSET               0x710000
74 #define CONFIG_ENV_SIZE                 (4 * 1024)
75 #define CONFIG_ENV_SECT_SIZE            (4 * 1024)
76 #endif /* CONFIG_ENV_IS_IN_SPI_FLASH */
77
78 #ifndef CONFIG_SPL_BUILD
79 #define CONFIG_MTD_DEVICE
80 #define CONFIG_MTD_PARTITIONS
81 #define MTDIDS_DEFAULT                  "nor0=ff705000.spi.0"
82 #endif /* CONFIG_SPL_BUILD */
83
84 #ifndef __ASSEMBLY__
85 unsigned int cm_get_qspi_controller_clk_hz(void);
86 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
87 #endif
88
89 #endif /* CONFIG_CADENCE_QSPI */
90
91 /*
92  * Boot arguments passed to the boot command. The value of
93  * CONFIG_BOOTARGS goes into the environment value "bootargs".
94  * Do note the value will override also the chosen node in FDT blob.
95  */
96 #define CONFIG_BOOTARGS "earlycon"
97 #define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" \
98                            "run mmcboot"
99
100 #define CONFIG_EXTRA_ENV_SETTINGS \
101         "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
102         "bootfile=Image\0" \
103         "fdt_addr=8000000\0" \
104         "fdtimage=socfpga_stratix10_socdk.dtb\0" \
105         "mmcroot=/dev/mmcblk0p2\0" \
106         "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
107                 " root=${mmcroot} rw rootwait;" \
108                 "booti ${loadaddr} - ${fdt_addr}\0" \
109         "mmcload=mmc rescan;" \
110                 "load mmc 0:1 ${loadaddr} ${bootfile};" \
111                 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
112         "linux_qspi_enable=if sf probe; then " \
113                 "echo Enabling QSPI at Linux DTB...;" \
114                 "fdt addr ${fdt_addr}; fdt resize;" \
115                 "fdt set /soc/spi@ff8d2000 status okay;" \
116                 "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
117                 " ${qspi_clock}; fi; \0" \
118         "scriptaddr=0x02100000\0" \
119         "scriptfile=u-boot.scr\0" \
120         "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
121                    "then source ${scriptaddr}; fi\0"
122
123 /*
124  * Generic Interrupt Controller Definitions
125  */
126 #define CONFIG_GICV2
127
128 /*
129  * External memory configurations
130  */
131 #define PHYS_SDRAM_1                    0x0
132 #define PHYS_SDRAM_1_SIZE               (1 * 1024 * 1024 * 1024)
133 #define CONFIG_SYS_SDRAM_BASE           0
134 #define CONFIG_SYS_MEMTEST_START        0
135 #define CONFIG_SYS_MEMTEST_END          PHYS_SDRAM_1_SIZE - 0x200000
136
137 /*
138  * SDRAM controller
139  */
140 #define CONFIG_ALTERA_SDRAM
141
142 /*
143  * Serial / UART configurations
144  */
145 #define CONFIG_SYS_NS16550_CLK          100000000
146 #define CONFIG_SYS_NS16550_MEM32
147
148 /*
149  * Timer & watchdog configurations
150  */
151 #define COUNTER_FREQUENCY               400000000
152
153 /*
154  * SDMMC configurations
155  */
156 #ifdef CONFIG_CMD_MMC
157 #define CONFIG_BOUNCE_BUFFER
158 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256
159 #endif
160 /*
161  * Flash configurations
162  */
163 #define CONFIG_SYS_MAX_FLASH_BANKS      1
164
165 /* Ethernet on SoC (EMAC) */
166 #if defined(CONFIG_CMD_NET)
167 #define CONFIG_DW_ALTDESCRIPTOR
168 #endif /* CONFIG_CMD_NET */
169
170 /*
171  * L4 Watchdog
172  */
173 #ifdef CONFIG_SPL_BUILD
174 #define CONFIG_HW_WATCHDOG
175 #define CONFIG_DESIGNWARE_WATCHDOG
176 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
177 #ifndef __ASSEMBLY__
178 unsigned int cm_get_l4_sys_free_clk_hz(void);
179 #define CONFIG_DW_WDT_CLOCK_KHZ         (cm_get_l4_sys_free_clk_hz() / 1000)
180 #endif
181 #define CONFIG_WATCHDOG_TIMEOUT_MSECS   3000
182 #endif
183
184 /*
185  * SPL memory layout
186  *
187  * On chip RAM
188  * 0xFFE0_0000 ...... Start of OCRAM
189  * SPL code, rwdata
190  * empty space
191  * 0xFFEx_xxxx ...... Top of stack (grows down)
192  * 0xFFEy_yyyy ...... Global Data
193  * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
194  * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
195  * 0xFFE3_FFFF ...... End of OCRAM
196  *
197  * SDRAM
198  * 0x0000_0000 ...... Start of SDRAM_1
199  * unused / empty space for image loading
200  * Size 64MB   ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
201  * Size 1MB    ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
202  * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
203  *
204  */
205 #define CONFIG_SPL_TEXT_BASE            CONFIG_SYS_INIT_RAM_ADDR
206 #define CONFIG_SPL_MAX_SIZE             CONFIG_SYS_INIT_RAM_SIZE
207 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
208 #define CONFIG_SPL_BSS_MAX_SIZE         0x100000        /* 1 MB */
209 #define CONFIG_SPL_BSS_START_ADDR       (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
210                                         - CONFIG_SPL_BSS_MAX_SIZE)
211 #define CONFIG_SYS_SPL_MALLOC_SIZE      (CONFIG_SYS_MALLOC_LEN)
212 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR \
213                                         - CONFIG_SYS_SPL_MALLOC_SIZE)
214 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x3C00000
215
216 /* SPL SDMMC boot support */
217 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
218 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot-dtb.img"
219
220 #endif  /* __CONFIG_H */