include/configs/socfpga_common.h

   1 /*
   2  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #ifndef __CONFIG_SOCFPGA_COMMON_H__
   7 #define __CONFIG_SOCFPGA_COMMON_H__
   8
   9 /* Virtual target or real hardware */
  10 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
  11
  12 /*
  13  * High level configuration
  14  */
  15 #define CONFIG_DISPLAY_BOARDINFO_LATE
  16 #define CONFIG_CLOCKS
  17
  18 #define CONFIG_CRC32_VERIFY
  19
  20 #define CONFIG_SYS_BOOTMAPSZ            (64 * 1024 * 1024)
  21
  22 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  23
  24 /* add target to build it automatically upon "make" */
  25 #define CONFIG_BUILD_TARGET             "u-boot-with-spl.sfp"
  26
  27 /*
  28  * Memory configurations
  29  */
  30 #define CONFIG_NR_DRAM_BANKS            1
  31 #define PHYS_SDRAM_1                    0x0
  32 #define CONFIG_SYS_MALLOC_LEN           (64 * 1024 * 1024)
  33 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_1
  34 #define CONFIG_SYS_MEMTEST_END          PHYS_SDRAM_1_SIZE
  35
  36 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFFF0000
  37 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
  38 #define CONFIG_SYS_INIT_SP_OFFSET               \
  39         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  40 #define CONFIG_SYS_INIT_SP_ADDR                 \
  41         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  42
  43 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  44 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
  45 #define CONFIG_SYS_TEXT_BASE            0x08000040
  46 #else
  47 #define CONFIG_SYS_TEXT_BASE            0x01000040
  48 #endif
  49
  50 /*
  51  * U-Boot general configurations
  52  */
  53 #define CONFIG_SYS_LONGHELP
  54 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O buffer size */
  55 #define CONFIG_SYS_PBSIZE       \
  56         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  57                                                 /* Print buffer size */
  58 #define CONFIG_SYS_MAXARGS      32              /* Max number of command args */
  59 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  60                                                 /* Boot argument buffer size */
  61 #define CONFIG_AUTO_COMPLETE                    /* Command auto complete */
  62 #define CONFIG_CMDLINE_EDITING                  /* Command history etc */
  63
  64 #ifndef CONFIG_SYS_HOSTNAME
  65 #define CONFIG_SYS_HOSTNAME     CONFIG_SYS_BOARD
  66 #endif
  67
  68 /*
  69  * Cache
  70  */
  71 #define CONFIG_SYS_L2_PL310
  72 #define CONFIG_SYS_PL310_BASE           SOCFPGA_MPUL2_ADDRESS
  73
  74 /*
  75  * EPCS/EPCQx1 Serial Flash Controller
  76  */
  77 #ifdef CONFIG_ALTERA_SPI
  78 #define CONFIG_SF_DEFAULT_SPEED         30000000
  79 /*
  80  * The base address is configurable in QSys, each board must specify the
  81  * base address based on it's particular FPGA configuration. Please note
  82  * that the address here is incremented by  0x400  from the Base address
  83  * selected in QSys, since the SPI registers are at offset +0x400.
  84  * #define CONFIG_SYS_SPI_BASE          0xff240400
  85  */
  86 #endif
  87
  88 /*
  89  * Ethernet on SoC (EMAC)
  90  */
  91 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
  92 #define CONFIG_DW_ALTDESCRIPTOR
  93 #define CONFIG_MII
  94 #define CONFIG_AUTONEG_TIMEOUT          (15 * CONFIG_SYS_HZ)
  95 #define CONFIG_PHY_GIGE
  96 #endif
  97
  98 /*
  99  * FPGA Driver
 100  */
 101 #ifdef CONFIG_CMD_FPGA
 102 #define CONFIG_FPGA
 103 #define CONFIG_FPGA_ALTERA
 104 #define CONFIG_FPGA_SOCFPGA
 105 #define CONFIG_FPGA_COUNT               1
 106 #endif
 107
 108 /*
 109  * L4 OSC1 Timer 0
 110  */
 111 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
 112 #define CONFIG_SYS_TIMERBASE            SOCFPGA_OSC1TIMER0_ADDRESS
 113 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 114 #define CONFIG_SYS_TIMER_COUNTER        (CONFIG_SYS_TIMERBASE + 0x4)
 115 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 116 #define CONFIG_SYS_TIMER_RATE           2400000
 117 #else
 118 #define CONFIG_SYS_TIMER_RATE           25000000
 119 #endif
 120
 121 /*
 122  * L4 Watchdog
 123  */
 124 #ifdef CONFIG_HW_WATCHDOG
 125 #define CONFIG_DESIGNWARE_WATCHDOG
 126 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 127 #define CONFIG_DW_WDT_CLOCK_KHZ         25000
 128 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS   30000
 129 #endif
 130
 131 /*
 132  * MMC Driver
 133  */
 134 #ifdef CONFIG_CMD_MMC
 135 #define CONFIG_BOUNCE_BUFFER
 136 /* FIXME */
 137 /* using smaller max blk cnt to avoid flooding the limited stack we have */
 138 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256     /* FIXME -- SPL only? */
 139 #endif
 140
 141 /*
 142  * NAND Support
 143  */
 144 #ifdef CONFIG_NAND_DENALI
 145 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 146 #define CONFIG_SYS_NAND_MAX_CHIPS       1
 147 #define CONFIG_SYS_NAND_ONFI_DETECTION
 148 #define CONFIG_NAND_DENALI_ECC_SIZE     512
 149 #define CONFIG_SYS_NAND_REGS_BASE       SOCFPGA_NANDREGS_ADDRESS
 150 #define CONFIG_SYS_NAND_DATA_BASE       SOCFPGA_NANDDATA_ADDRESS
 151 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_DATA_BASE + 0x10)
 152 #endif
 153
 154 /*
 155  * I2C support
 156  */
 157 #define CONFIG_SYS_I2C
 158 #define CONFIG_SYS_I2C_BUS_MAX          4
 159 #define CONFIG_SYS_I2C_BASE             SOCFPGA_I2C0_ADDRESS
 160 #define CONFIG_SYS_I2C_BASE1            SOCFPGA_I2C1_ADDRESS
 161 #define CONFIG_SYS_I2C_BASE2            SOCFPGA_I2C2_ADDRESS
 162 #define CONFIG_SYS_I2C_BASE3            SOCFPGA_I2C3_ADDRESS
 163 /* Using standard mode which the speed up to 100Kb/s */
 164 #define CONFIG_SYS_I2C_SPEED            100000
 165 #define CONFIG_SYS_I2C_SPEED1           100000
 166 #define CONFIG_SYS_I2C_SPEED2           100000
 167 #define CONFIG_SYS_I2C_SPEED3           100000
 168 /* Address of device when used as slave */
 169 #define CONFIG_SYS_I2C_SLAVE            0x02
 170 #define CONFIG_SYS_I2C_SLAVE1           0x02
 171 #define CONFIG_SYS_I2C_SLAVE2           0x02
 172 #define CONFIG_SYS_I2C_SLAVE3           0x02
 173 #ifndef __ASSEMBLY__
 174 /* Clock supplied to I2C controller in unit of MHz */
 175 unsigned int cm_get_l4_sp_clk_hz(void);
 176 #define IC_CLK                          (cm_get_l4_sp_clk_hz() / 1000000)
 177 #endif
 178
 179 /*
 180  * QSPI support
 181  */
 182 /* Enable multiple SPI NOR flash manufacturers */
 183 #ifndef CONFIG_SPL_BUILD
 184 #define CONFIG_SPI_FLASH_MTD
 185 #define CONFIG_CMD_MTDPARTS
 186 #define CONFIG_MTD_DEVICE
 187 #define CONFIG_MTD_PARTITIONS
 188 #define MTDIDS_DEFAULT                  "nor0=ff705000.spi.0"
 189 #endif
 190 /* QSPI reference clock */
 191 #ifndef __ASSEMBLY__
 192 unsigned int cm_get_qspi_controller_clk_hz(void);
 193 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
 194 #endif
 195 #define CONFIG_CQSPI_DECODER            0
 196 #define CONFIG_BOUNCE_BUFFER
 197
 198 /*
 199  * Designware SPI support
 200  */
 201
 202 /*
 203  * Serial Driver
 204  */
 205 #define CONFIG_SYS_NS16550_SERIAL
 206 #define CONFIG_SYS_NS16550_REG_SIZE     -4
 207 #define CONFIG_SYS_NS16550_COM1         SOCFPGA_UART0_ADDRESS
 208 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 209 #define CONFIG_SYS_NS16550_CLK          1000000
 210 #else
 211 #define CONFIG_SYS_NS16550_CLK          100000000
 212 #endif
 213 #define CONFIG_CONS_INDEX               1
 214
 215 /*
 216  * USB
 217  */
 218 #ifdef CONFIG_CMD_USB
 219 #define CONFIG_USB_DWC2
 220 #endif
 221
 222 /*
 223  * USB Gadget (DFU, UMS)
 224  */
 225 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
 226 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 227
 228 #define CONFIG_SYS_DFU_DATA_BUF_SIZE    (16 * 1024 * 1024)
 229 #define DFU_DEFAULT_POLL_TIMEOUT        300
 230
 231 /* USB IDs */
 232 #define CONFIG_G_DNL_UMS_VENDOR_NUM     0x0525
 233 #define CONFIG_G_DNL_UMS_PRODUCT_NUM    0xA4A5
 234 #endif
 235
 236 /*
 237  * U-Boot environment
 238  */
 239 #if !defined(CONFIG_ENV_SIZE)
 240 #define CONFIG_ENV_SIZE                 4096
 241 #endif
 242
 243 /* Environment for SDMMC boot */
 244 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
 245 #define CONFIG_SYS_MMC_ENV_DEV          0       /* device 0 */
 246 #define CONFIG_ENV_OFFSET               512     /* just after the MBR */
 247 #endif
 248
 249 /* Environment for QSPI boot */
 250 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
 251 #define CONFIG_ENV_OFFSET               0x00100000
 252 #define CONFIG_ENV_SECT_SIZE            (64 * 1024)
 253 #endif
 254
 255 /*
 256  * mtd partitioning for serial NOR flash
 257  *
 258  * device nor0 <ff705000.spi.0>, # parts = 6
 259  * #: name                size            offset          mask_flags
 260  * 0: u-boot              0x00100000      0x00000000      0
 261  * 1: env1                0x00040000      0x00100000      0
 262  * 2: env2                0x00040000      0x00140000      0
 263  * 3: UBI                 0x03e80000      0x00180000      0
 264  * 4: boot                0x00e80000      0x00180000      0
 265  * 5: rootfs              0x01000000      0x01000000      0
 266  *
 267  */
 268 #if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT)
 269 #define MTDPARTS_DEFAULT        "mtdparts=ff705000.spi.0:"\
 270                                 "1m(u-boot),"           \
 271                                 "256k(env1),"           \
 272                                 "256k(env2),"           \
 273                                 "14848k(boot),"         \
 274                                 "16m(rootfs),"          \
 275                                 "-@1536k(UBI)\0"
 276 #endif
 277
 278 /* UBI and UBIFS support */
 279 #if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND)
 280 #define CONFIG_CMD_UBIFS
 281 #define CONFIG_RBTREE
 282 #define CONFIG_LZO
 283 #endif
 284
 285 /*
 286  * SPL
 287  *
 288  * SRAM Memory layout:
 289  *
 290  * 0xFFFF_0000 ...... Start of SRAM
 291  * 0xFFFF_xxxx ...... Top of stack (grows down)
 292  * 0xFFFF_yyyy ...... Malloc area
 293  * 0xFFFF_zzzz ...... Global Data
 294  * 0xFFFF_FF00 ...... End of SRAM
 295  */
 296 #define CONFIG_SPL_FRAMEWORK
 297 #define CONFIG_SPL_TEXT_BASE            CONFIG_SYS_INIT_RAM_ADDR
 298 #define CONFIG_SPL_MAX_SIZE             (64 * 1024)
 299
 300 /* SPL SDMMC boot support */
 301 #ifdef CONFIG_SPL_MMC_SUPPORT
 302 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
 303 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      2
 304 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot-dtb.img"
 305 #endif
 306 #endif
 307
 308 /* SPL QSPI boot support */
 309 #ifdef CONFIG_SPL_SPI_SUPPORT
 310 #define CONFIG_SPL_SPI_LOAD
 311 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x40000
 312 #endif
 313
 314 /* SPL NAND boot support */
 315 #ifdef CONFIG_SPL_NAND_SUPPORT
 316 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 317 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 318 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
 319 #endif
 320
 321 /*
 322  * Stack setup
 323  */
 324 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 325
 326 #endif  /* __CONFIG_SOCFPGA_COMMON_H__ */