1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2012 Altera Corporation <www.altera.com>
5 #ifndef __CONFIG_SOCFPGA_COMMON_H__
6 #define __CONFIG_SOCFPGA_COMMON_H__
9 * High level configuration
13 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
15 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
18 * Memory configurations
20 #define PHYS_SDRAM_1 0x0
21 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
22 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
23 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
24 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
25 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
26 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
27 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
28 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
29 /* SPL memory allocation configuration, this is for FAT implementation */
30 #ifndef CONFIG_SYS_SPL_MALLOC_SIZE
31 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000
33 #define CONFIG_SYS_INIT_RAM_SIZE (0x40000 - CONFIG_SYS_SPL_MALLOC_SIZE)
34 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \
35 CONFIG_SYS_INIT_RAM_SIZE)
39 * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
40 * SRAM as bootcounter storage. Make sure to not put the stack directly
41 * at this address to not overwrite the bootcounter by checking, if the
42 * bootcounter address is located in the internal SRAM.
44 #if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
45 (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
46 CONFIG_SYS_INIT_RAM_SIZE)))
47 #define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR
49 #define CONFIG_SPL_STACK \
50 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
54 * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
55 * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
56 * in U-Boot pre-reloc is higher than in SPL.
58 #if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR
59 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR
61 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
64 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
67 * U-Boot general configurations
69 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
70 /* Print buffer size */
71 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
72 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
73 /* Boot argument buffer size */
75 #ifndef CONFIG_SYS_HOSTNAME
76 #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD
82 #define CONFIG_SYS_L2_PL310
83 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
86 * EPCS/EPCQx1 Serial Flash Controller
88 #ifdef CONFIG_ALTERA_SPI
90 * The base address is configurable in QSys, each board must specify the
91 * base address based on it's particular FPGA configuration. Please note
92 * that the address here is incremented by 0x400 from the Base address
93 * selected in QSys, since the SPI registers are at offset +0x400.
94 * #define CONFIG_SYS_SPI_BASE 0xff240400
99 * Ethernet on SoC (EMAC)
101 #ifdef CONFIG_CMD_NET
102 #define CONFIG_DW_ALTDESCRIPTOR
108 #ifdef CONFIG_CMD_FPGA
109 #define CONFIG_FPGA_COUNT 1
116 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
117 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
118 #define CONFIG_SYS_TIMER_COUNTS_DOWN
119 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
120 #define CONFIG_SYS_TIMER_RATE 25000000
126 #ifdef CONFIG_HW_WATCHDOG
127 #define CONFIG_DESIGNWARE_WATCHDOG
128 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
129 #define CONFIG_DW_WDT_CLOCK_KHZ 25000
130 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000
136 #ifdef CONFIG_CMD_MMC
138 /* using smaller max blk cnt to avoid flooding the limited stack we have */
139 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
145 #ifdef CONFIG_NAND_DENALI
146 #define CONFIG_SYS_MAX_NAND_DEVICE 1
147 #define CONFIG_SYS_NAND_ONFI_DETECTION
148 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
149 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
155 /* Enable multiple SPI NOR flash manufacturers */
156 #ifndef CONFIG_SPL_BUILD
157 #define CONFIG_SPI_FLASH_MTD
159 /* QSPI reference clock */
161 unsigned int cm_get_qspi_controller_clk_hz(void);
162 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
166 * Designware SPI support
172 #define CONFIG_SYS_NS16550_SERIAL
179 * USB Gadget (DFU, UMS)
181 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
182 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024)
183 #define DFU_DEFAULT_POLL_TIMEOUT 300
186 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
187 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
193 #if !defined(CONFIG_ENV_SIZE)
194 #define CONFIG_ENV_SIZE (8 * 1024)
197 /* Environment for SDMMC boot */
198 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
199 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
200 #define CONFIG_ENV_OFFSET (34 * 512) /* just after the GPT */
203 /* Environment for QSPI boot */
204 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
205 #define CONFIG_ENV_OFFSET 0x00100000
206 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
210 * mtd partitioning for serial NOR flash
212 * device nor0 <ff705000.spi.0>, # parts = 6
213 * #: name size offset mask_flags
214 * 0: u-boot 0x00100000 0x00000000 0
215 * 1: env1 0x00040000 0x00100000 0
216 * 2: env2 0x00040000 0x00140000 0
217 * 3: UBI 0x03e80000 0x00180000 0
218 * 4: boot 0x00e80000 0x00180000 0
219 * 5: rootfs 0x01000000 0x01000000 0
226 * SRAM Memory layout for gen 5:
228 * 0xFFFF_0000 ...... Start of SRAM
229 * 0xFFFF_xxxx ...... Top of stack (grows down)
230 * 0xFFFF_yyyy ...... Global Data
231 * 0xFFFF_zzzz ...... Malloc area
232 * 0xFFFF_FFFF ...... End of SRAM
234 * SRAM Memory layout for Arria 10:
235 * 0xFFE0_0000 ...... Start of SRAM (bottom)
236 * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
237 * 0xFFEy_yyyy ...... Global Data
238 * 0xFFEz_zzzz ...... Malloc area (grows up to top)
239 * 0xFFE3_FFFF ...... End of SRAM (top)
241 #ifndef CONFIG_SPL_TEXT_BASE
242 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
243 #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
246 /* SPL SDMMC boot support */
247 #ifdef CONFIG_SPL_MMC_SUPPORT
248 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
249 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
250 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
253 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
254 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
258 /* SPL QSPI boot support */
259 #ifdef CONFIG_SPL_SPI_SUPPORT
260 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
261 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
262 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
263 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000
267 /* SPL NAND boot support */
268 #ifdef CONFIG_SPL_NAND_SUPPORT
269 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
270 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
271 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
272 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000
276 /* Extra Environment */
277 #ifndef CONFIG_SPL_BUILD
279 #ifdef CONFIG_CMD_DHCP
280 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
282 #define BOOT_TARGET_DEVICES_DHCP(func)
285 #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
286 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
288 #define BOOT_TARGET_DEVICES_PXE(func)
291 #ifdef CONFIG_CMD_MMC
292 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
294 #define BOOT_TARGET_DEVICES_MMC(func)
297 #define BOOT_TARGET_DEVICES(func) \
298 BOOT_TARGET_DEVICES_MMC(func) \
299 BOOT_TARGET_DEVICES_PXE(func) \
300 BOOT_TARGET_DEVICES_DHCP(func)
302 #include <config_distro_bootcmd.h>
304 #ifndef CONFIG_EXTRA_ENV_SETTINGS
305 #define CONFIG_EXTRA_ENV_SETTINGS \
306 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
307 "bootm_size=0xa000000\0" \
308 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
309 "fdt_addr_r=0x02000000\0" \
310 "scriptaddr=0x02100000\0" \
311 "pxefile_addr_r=0x02200000\0" \
312 "ramdisk_addr_r=0x02300000\0" \
313 "socfpga_legacy_reset_compat=1\0" \
319 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */