include/configs/socfpga_common.h

   1 /*
   2  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #ifndef __CONFIG_SOCFPGA_COMMON_H__
   7 #define __CONFIG_SOCFPGA_COMMON_H__
   8
   9 /* Virtual target or real hardware */
  10 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
  11
  12 /*
  13  * High level configuration
  14  */
  15 #define CONFIG_DISPLAY_BOARDINFO_LATE
  16 #define CONFIG_CLOCKS
  17
  18 #define CONFIG_SYS_BOOTMAPSZ            (64 * 1024 * 1024)
  19
  20 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  21
  22 /* add target to build it automatically upon "make" */
  23 #define CONFIG_BUILD_TARGET             "u-boot-with-spl.sfp"
  24
  25 /*
  26  * Memory configurations
  27  */
  28 #define CONFIG_NR_DRAM_BANKS            1
  29 #define PHYS_SDRAM_1                    0x0
  30 #define CONFIG_SYS_MALLOC_LEN           (64 * 1024 * 1024)
  31 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_1
  32 #define CONFIG_SYS_MEMTEST_END          PHYS_SDRAM_1_SIZE
  33 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  34 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFFF0000
  35 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
  36 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
  37 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFE00000
  38 #define CONFIG_SYS_INIT_RAM_SIZE        0x40000 /* 256KB */
  39 #endif
  40 #define CONFIG_SYS_INIT_SP_OFFSET               \
  41         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  42 #define CONFIG_SYS_INIT_SP_ADDR                 \
  43         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  44
  45 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  46 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
  47 #define CONFIG_SYS_TEXT_BASE            0x08000040
  48 #else
  49 #define CONFIG_SYS_TEXT_BASE            0x01000040
  50 #endif
  51
  52 /*
  53  * U-Boot general configurations
  54  */
  55 #define CONFIG_SYS_LONGHELP
  56 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O buffer size */
  57                                                 /* Print buffer size */
  58 #define CONFIG_SYS_MAXARGS      32              /* Max number of command args */
  59 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  60                                                 /* Boot argument buffer size */
  61 #define CONFIG_AUTO_COMPLETE                    /* Command auto complete */
  62 #define CONFIG_CMDLINE_EDITING                  /* Command history etc */
  63
  64 #ifndef CONFIG_SYS_HOSTNAME
  65 #define CONFIG_SYS_HOSTNAME     CONFIG_SYS_BOARD
  66 #endif
  67
  68 #define CONFIG_CMD_PXE
  69 #define CONFIG_MENU
  70
  71 /*
  72  * Cache
  73  */
  74 #define CONFIG_SYS_L2_PL310
  75 #define CONFIG_SYS_PL310_BASE           SOCFPGA_MPUL2_ADDRESS
  76
  77 /*
  78  * EPCS/EPCQx1 Serial Flash Controller
  79  */
  80 #ifdef CONFIG_ALTERA_SPI
  81 #define CONFIG_SF_DEFAULT_SPEED         30000000
  82 /*
  83  * The base address is configurable in QSys, each board must specify the
  84  * base address based on it's particular FPGA configuration. Please note
  85  * that the address here is incremented by  0x400  from the Base address
  86  * selected in QSys, since the SPI registers are at offset +0x400.
  87  * #define CONFIG_SYS_SPI_BASE          0xff240400
  88  */
  89 #endif
  90
  91 /*
  92  * Ethernet on SoC (EMAC)
  93  */
  94 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
  95 #define CONFIG_DW_ALTDESCRIPTOR
  96 #define CONFIG_MII
  97 #define CONFIG_AUTONEG_TIMEOUT          (15 * CONFIG_SYS_HZ)
  98 #endif
  99
 100 /*
 101  * FPGA Driver
 102  */
 103 #ifdef CONFIG_CMD_FPGA
 104 #define CONFIG_FPGA_COUNT               1
 105 #endif
 106
 107 /*
 108  * L4 OSC1 Timer 0
 109  */
 110 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
 111 #define CONFIG_SYS_TIMERBASE            SOCFPGA_OSC1TIMER0_ADDRESS
 112 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 113 #define CONFIG_SYS_TIMER_COUNTER        (CONFIG_SYS_TIMERBASE + 0x4)
 114 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 115 #define CONFIG_SYS_TIMER_RATE           2400000
 116 #else
 117 #define CONFIG_SYS_TIMER_RATE           25000000
 118 #endif
 119
 120 /*
 121  * L4 Watchdog
 122  */
 123 #ifdef CONFIG_HW_WATCHDOG
 124 #define CONFIG_DESIGNWARE_WATCHDOG
 125 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 126 #define CONFIG_DW_WDT_CLOCK_KHZ         25000
 127 #define CONFIG_WATCHDOG_TIMEOUT_MSECS   30000
 128 #endif
 129
 130 /*
 131  * MMC Driver
 132  */
 133 #ifdef CONFIG_CMD_MMC
 134 #define CONFIG_BOUNCE_BUFFER
 135 /* FIXME */
 136 /* using smaller max blk cnt to avoid flooding the limited stack we have */
 137 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256     /* FIXME -- SPL only? */
 138 #endif
 139
 140 /*
 141  * NAND Support
 142  */
 143 #ifdef CONFIG_NAND_DENALI
 144 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 145 #define CONFIG_SYS_NAND_MAX_CHIPS       1
 146 #define CONFIG_SYS_NAND_ONFI_DETECTION
 147 #define CONFIG_NAND_DENALI_ECC_SIZE     512
 148 #define CONFIG_SYS_NAND_REGS_BASE       SOCFPGA_NANDREGS_ADDRESS
 149 #define CONFIG_SYS_NAND_DATA_BASE       SOCFPGA_NANDDATA_ADDRESS
 150 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_DATA_BASE + 0x10)
 151 #endif
 152
 153 /*
 154  * I2C support
 155  */
 156 #define CONFIG_SYS_I2C
 157 #define CONFIG_SYS_I2C_BASE             SOCFPGA_I2C0_ADDRESS
 158 #define CONFIG_SYS_I2C_BASE1            SOCFPGA_I2C1_ADDRESS
 159 #define CONFIG_SYS_I2C_BASE2            SOCFPGA_I2C2_ADDRESS
 160 #define CONFIG_SYS_I2C_BASE3            SOCFPGA_I2C3_ADDRESS
 161 /* Using standard mode which the speed up to 100Kb/s */
 162 #define CONFIG_SYS_I2C_SPEED            100000
 163 #define CONFIG_SYS_I2C_SPEED1           100000
 164 #define CONFIG_SYS_I2C_SPEED2           100000
 165 #define CONFIG_SYS_I2C_SPEED3           100000
 166 /* Address of device when used as slave */
 167 #define CONFIG_SYS_I2C_SLAVE            0x02
 168 #define CONFIG_SYS_I2C_SLAVE1           0x02
 169 #define CONFIG_SYS_I2C_SLAVE2           0x02
 170 #define CONFIG_SYS_I2C_SLAVE3           0x02
 171 #ifndef __ASSEMBLY__
 172 /* Clock supplied to I2C controller in unit of MHz */
 173 unsigned int cm_get_l4_sp_clk_hz(void);
 174 #define IC_CLK                          (cm_get_l4_sp_clk_hz() / 1000000)
 175 #endif
 176
 177 /*
 178  * QSPI support
 179  */
 180 /* Enable multiple SPI NOR flash manufacturers */
 181 #ifndef CONFIG_SPL_BUILD
 182 #define CONFIG_SPI_FLASH_MTD
 183 #define CONFIG_MTD_DEVICE
 184 #define CONFIG_MTD_PARTITIONS
 185 #define MTDIDS_DEFAULT                  "nor0=ff705000.spi.0"
 186 #endif
 187 /* QSPI reference clock */
 188 #ifndef __ASSEMBLY__
 189 unsigned int cm_get_qspi_controller_clk_hz(void);
 190 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
 191 #endif
 192 #define CONFIG_CQSPI_DECODER            0
 193 #define CONFIG_BOUNCE_BUFFER
 194
 195 /*
 196  * Designware SPI support
 197  */
 198
 199 /*
 200  * Serial Driver
 201  */
 202 #define CONFIG_SYS_NS16550_SERIAL
 203 #define CONFIG_SYS_NS16550_REG_SIZE     -4
 204 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 205 #define CONFIG_SYS_NS16550_CLK          1000000
 206 #elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
 207 #define CONFIG_SYS_NS16550_COM1         SOCFPGA_UART0_ADDRESS
 208 #define CONFIG_SYS_NS16550_CLK          100000000
 209 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 210 #define CONFIG_SYS_NS16550_COM1        SOCFPGA_UART1_ADDRESS
 211 #define CONFIG_SYS_NS16550_CLK          50000000
 212 #endif
 213 #define CONFIG_CONS_INDEX               1
 214
 215 /*
 216  * USB
 217  */
 218
 219 /*
 220  * USB Gadget (DFU, UMS)
 221  */
 222 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
 223 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 224
 225 #define CONFIG_SYS_DFU_DATA_BUF_SIZE    (16 * 1024 * 1024)
 226 #define DFU_DEFAULT_POLL_TIMEOUT        300
 227
 228 /* USB IDs */
 229 #define CONFIG_G_DNL_UMS_VENDOR_NUM     0x0525
 230 #define CONFIG_G_DNL_UMS_PRODUCT_NUM    0xA4A5
 231 #endif
 232
 233 /*
 234  * U-Boot environment
 235  */
 236 #if !defined(CONFIG_ENV_SIZE)
 237 #define CONFIG_ENV_SIZE                 (8 * 1024)
 238 #endif
 239
 240 /* Environment for SDMMC boot */
 241 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
 242 #define CONFIG_SYS_MMC_ENV_DEV          0 /* device 0 */
 243 #define CONFIG_ENV_OFFSET               (34 * 512) /* just after the GPT */
 244 #endif
 245
 246 /* Environment for QSPI boot */
 247 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
 248 #define CONFIG_ENV_OFFSET               0x00100000
 249 #define CONFIG_ENV_SECT_SIZE            (64 * 1024)
 250 #endif
 251
 252 /*
 253  * mtd partitioning for serial NOR flash
 254  *
 255  * device nor0 <ff705000.spi.0>, # parts = 6
 256  * #: name                size            offset          mask_flags
 257  * 0: u-boot              0x00100000      0x00000000      0
 258  * 1: env1                0x00040000      0x00100000      0
 259  * 2: env2                0x00040000      0x00140000      0
 260  * 3: UBI                 0x03e80000      0x00180000      0
 261  * 4: boot                0x00e80000      0x00180000      0
 262  * 5: rootfs              0x01000000      0x01000000      0
 263  *
 264  */
 265 #if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT)
 266 #define MTDPARTS_DEFAULT        "mtdparts=ff705000.spi.0:"\
 267                                 "1m(u-boot),"           \
 268                                 "256k(env1),"           \
 269                                 "256k(env2),"           \
 270                                 "14848k(boot),"         \
 271                                 "16m(rootfs),"          \
 272                                 "-@1536k(UBI)\0"
 273 #endif
 274
 275 /*
 276  * SPL
 277  *
 278  * SRAM Memory layout:
 279  *
 280  * 0xFFFF_0000 ...... Start of SRAM
 281  * 0xFFFF_xxxx ...... Top of stack (grows down)
 282  * 0xFFFF_yyyy ...... Malloc area
 283  * 0xFFFF_zzzz ...... Global Data
 284  * 0xFFFF_FF00 ...... End of SRAM
 285  */
 286 #define CONFIG_SPL_FRAMEWORK
 287 #define CONFIG_SPL_TEXT_BASE            CONFIG_SYS_INIT_RAM_ADDR
 288 #define CONFIG_SPL_MAX_SIZE             CONFIG_SYS_INIT_RAM_SIZE
 289
 290 /* SPL SDMMC boot support */
 291 #ifdef CONFIG_SPL_MMC_SUPPORT
 292 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
 293 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot-dtb.img"
 294 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 295 #endif
 296 #else
 297 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
 298 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION      1
 299 #endif
 300 #endif
 301
 302 /* SPL QSPI boot support */
 303 #ifdef CONFIG_SPL_SPI_SUPPORT
 304 #define CONFIG_SPL_SPI_LOAD
 305 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x40000
 306 #endif
 307
 308 /* SPL NAND boot support */
 309 #ifdef CONFIG_SPL_NAND_SUPPORT
 310 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 311 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 312 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
 313 #endif
 314
 315 /*
 316  * Stack setup
 317  */
 318 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 319
 320 /* Extra Environment */
 321 #ifndef CONFIG_SPL_BUILD
 322 #include <config_distro_defaults.h>
 323
 324 #ifdef CONFIG_CMD_PXE
 325 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
 326 #else
 327 #define BOOT_TARGET_DEVICES_PXE(func)
 328 #endif
 329
 330 #ifdef CONFIG_CMD_MMC
 331 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
 332 #else
 333 #define BOOT_TARGET_DEVICES_MMC(func)
 334 #endif
 335
 336 #define BOOT_TARGET_DEVICES(func) \
 337         BOOT_TARGET_DEVICES_MMC(func) \
 338         BOOT_TARGET_DEVICES_PXE(func) \
 339         func(DHCP, dhcp, na)
 340
 341 #include <config_distro_bootcmd.h>
 342
 343 #ifndef CONFIG_EXTRA_ENV_SETTINGS
 344 #define CONFIG_EXTRA_ENV_SETTINGS \
 345         "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
 346         "bootm_size=0xa000000\0" \
 347         "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
 348         "fdt_addr_r=0x02000000\0" \
 349         "scriptaddr=0x02100000\0" \
 350         "pxefile_addr_r=0x02200000\0" \
 351         "ramdisk_addr_r=0x02300000\0" \
 352         BOOTENV
 353
 354 #endif
 355 #endif
 356
 357 #endif  /* __CONFIG_SOCFPGA_COMMON_H__ */