1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2012 Altera Corporation <www.altera.com>
5 #ifndef __CONFIG_SOCFPGA_COMMON_H__
6 #define __CONFIG_SOCFPGA_COMMON_H__
9 * High level configuration
13 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
16 * Memory configurations
18 #define PHYS_SDRAM_1 0x0
19 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
20 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
21 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
22 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
23 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
24 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
25 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
26 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
27 /* SPL memory allocation configuration, this is for FAT implementation */
28 #ifndef CONFIG_SYS_SPL_MALLOC_SIZE
29 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000
31 #define CONFIG_SYS_INIT_RAM_SIZE (0x40000 - CONFIG_SYS_SPL_MALLOC_SIZE)
32 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \
33 CONFIG_SYS_INIT_RAM_SIZE)
37 * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
38 * SRAM as bootcounter storage. Make sure to not put the stack directly
39 * at this address to not overwrite the bootcounter by checking, if the
40 * bootcounter address is located in the internal SRAM.
42 #if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
43 (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
44 CONFIG_SYS_INIT_RAM_SIZE)))
45 #define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR
47 #define CONFIG_SPL_STACK \
48 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
52 * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
53 * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
54 * in U-Boot pre-reloc is higher than in SPL.
56 #if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR
57 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR
59 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
62 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
65 * U-Boot general configurations
67 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
68 /* Print buffer size */
69 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
70 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
71 /* Boot argument buffer size */
76 #define CONFIG_SYS_L2_PL310
77 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
80 * Ethernet on SoC (EMAC)
83 #define CONFIG_DW_ALTDESCRIPTOR
89 #ifdef CONFIG_CMD_FPGA
90 #define CONFIG_FPGA_COUNT 1
97 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
98 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
99 #define CONFIG_SYS_TIMER_COUNTS_DOWN
100 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
101 #define CONFIG_SYS_TIMER_RATE 25000000
107 #ifdef CONFIG_HW_WATCHDOG
108 #define CONFIG_DESIGNWARE_WATCHDOG
109 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
110 #define CONFIG_DW_WDT_CLOCK_KHZ 25000
116 #ifdef CONFIG_CMD_MMC
118 /* using smaller max blk cnt to avoid flooding the limited stack we have */
119 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
125 #ifdef CONFIG_NAND_DENALI
126 #define CONFIG_SYS_MAX_NAND_DEVICE 1
127 #define CONFIG_SYS_NAND_ONFI_DETECTION
128 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
129 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
135 /* Enable multiple SPI NOR flash manufacturers */
136 #ifndef CONFIG_SPL_BUILD
137 #define CONFIG_SPI_FLASH_MTD
139 /* QSPI reference clock */
141 unsigned int cm_get_qspi_controller_clk_hz(void);
142 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
150 * USB Gadget (DFU, UMS)
152 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
153 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024)
154 #define DFU_DEFAULT_POLL_TIMEOUT 300
157 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
158 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
164 #if !defined(CONFIG_ENV_SIZE)
165 #define CONFIG_ENV_SIZE (8 * 1024)
168 /* Environment for SDMMC boot */
169 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
170 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
171 #define CONFIG_ENV_OFFSET (34 * 512) /* just after the GPT */
174 /* Environment for QSPI boot */
175 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
176 #define CONFIG_ENV_OFFSET 0x00100000
177 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
183 * SRAM Memory layout for gen 5:
185 * 0xFFFF_0000 ...... Start of SRAM
186 * 0xFFFF_xxxx ...... Top of stack (grows down)
187 * 0xFFFF_yyyy ...... Global Data
188 * 0xFFFF_zzzz ...... Malloc area
189 * 0xFFFF_FFFF ...... End of SRAM
191 * SRAM Memory layout for Arria 10:
192 * 0xFFE0_0000 ...... Start of SRAM (bottom)
193 * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
194 * 0xFFEy_yyyy ...... Global Data
195 * 0xFFEz_zzzz ...... Malloc area (grows up to top)
196 * 0xFFE3_FFFF ...... End of SRAM (top)
198 #ifndef CONFIG_SPL_TEXT_BASE
199 #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
202 /* SPL SDMMC boot support */
203 #ifdef CONFIG_SPL_MMC_SUPPORT
204 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
205 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
206 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
209 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
210 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
214 /* SPL QSPI boot support */
216 /* SPL NAND boot support */
217 #ifdef CONFIG_SPL_NAND_SUPPORT
218 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
219 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
220 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
221 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000
225 /* Extra Environment */
226 #ifndef CONFIG_SPL_BUILD
228 #ifdef CONFIG_CMD_DHCP
229 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
231 #define BOOT_TARGET_DEVICES_DHCP(func)
234 #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
235 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
237 #define BOOT_TARGET_DEVICES_PXE(func)
240 #ifdef CONFIG_CMD_MMC
241 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
243 #define BOOT_TARGET_DEVICES_MMC(func)
246 #define BOOT_TARGET_DEVICES(func) \
247 BOOT_TARGET_DEVICES_MMC(func) \
248 BOOT_TARGET_DEVICES_PXE(func) \
249 BOOT_TARGET_DEVICES_DHCP(func)
251 #include <config_distro_bootcmd.h>
253 #ifndef CONFIG_EXTRA_ENV_SETTINGS
254 #define CONFIG_EXTRA_ENV_SETTINGS \
255 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
256 "bootm_size=0xa000000\0" \
257 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
258 "fdt_addr_r=0x02000000\0" \
259 "scriptaddr=0x02100000\0" \
260 "pxefile_addr_r=0x02200000\0" \
261 "ramdisk_addr_r=0x02300000\0" \
262 "socfpga_legacy_reset_compat=1\0" \
268 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */