3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 * Gary Jennejohn <gj@denx.de>
6 * David Mueller <d.mueller@elsoft.ch>
9 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
11 * Configuation settings for the SAMSUNG SMDK6400(mDirac-III) board.
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 * High Level Configuration Options
39 #define CONFIG_S3C6400 1 /* in a SAMSUNG S3C6400 SoC */
40 #define CONFIG_S3C64XX 1 /* in a SAMSUNG S3C64XX Family */
41 #define CONFIG_SMDK6400 1 /* on a SAMSUNG SMDK6400 Board */
43 #define CFG_SDRAM_BASE 0x50000000
45 /* input clock of PLL: SMDK6400 has 12MHz input clock */
46 #define CONFIG_SYS_CLK_FREQ 12000000
48 #if !defined(CONFIG_NAND_SPL) && (TEXT_BASE >= 0xc0000000)
49 #define CONFIG_ENABLE_MMU
52 #define CONFIG_MEMORY_UPPER_CODE
54 #define CONFIG_SETUP_MEMORY_TAGS
55 #define CONFIG_CMDLINE_TAG
56 #define CONFIG_INITRD_TAG
59 * Architecture magic and machine type
61 #define MACH_TYPE 1270
63 #define CONFIG_DISPLAY_CPUINFO
64 #define CONFIG_DISPLAY_BOARDINFO
66 #undef CONFIG_SKIP_RELOCATE_UBOOT
69 * Size of malloc() pool
71 #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 1024 * 1024)
72 #define CFG_GBL_DATA_SIZE 128 /* size in bytes for initial data */
77 #define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
78 #define CS8900_BASE 0x18800300
79 #define CS8900_BUS16 1 /* follow the Linux driver */
82 * select serial console configuration
84 #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK6400 */
86 #define CFG_HUSH_PARSER /* use "hush" command parser */
87 #ifdef CFG_HUSH_PARSER
88 #define CFG_PROMPT_HUSH_PS2 "> "
91 #define CONFIG_CMDLINE_EDITING
93 /* allow to overwrite serial and ethaddr */
94 #define CONFIG_ENV_OVERWRITE
96 #define CONFIG_BAUDRATE 115200
98 /***********************************************************
100 ***********************************************************/
101 #include <config_cmd_default.h>
103 #define CONFIG_CMD_CACHE
104 #define CONFIG_CMD_REGINFO
105 #define CONFIG_CMD_LOADS
106 #define CONFIG_CMD_LOADB
107 #define CONFIG_CMD_ENV
108 #define CONFIG_CMD_NAND
109 #if defined(CONFIG_BOOT_ONENAND)
110 #define CONFIG_CMD_ONENAND
112 #define CONFIG_CMD_PING
113 #define CONFIG_CMD_ELF
114 #define CONFIG_CMD_FAT
115 #define CONFIG_CMD_EXT2
117 #define CONFIG_BOOTDELAY 3
119 #define CONFIG_ZERO_BOOTDELAY_CHECK
121 #if (CONFIG_COMMANDS & CONFIG_CMD_KGDB)
122 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
123 #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
127 * Miscellaneous configurable options
129 #define CFG_LONGHELP /* undef to save memory */
130 #define CFG_PROMPT "SMDK6400 # " /* Monitor Command Prompt */
131 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
132 #define CFG_PBSIZE 384 /* Print Buffer Size */
133 #define CFG_MAXARGS 16 /* max number of command args */
134 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
136 #define CFG_MEMTEST_START CFG_SDRAM_BASE /* memtest works on */
137 #define CFG_MEMTEST_END (CFG_SDRAM_BASE + 0x7e00000) /* 126MB in DRAM */
139 #define CFG_LOAD_ADDR CFG_SDRAM_BASE /* default load address */
143 /* valid baudrates */
144 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
146 /*-----------------------------------------------------------------------
149 * The stack sizes are set up in start.S using the settings below
151 #define CONFIG_STACKSIZE 0x40000 /* regular stack 256KB */
153 /**********************************
154 Support Clock Settings
155 **********************************
157 ----------------------------------
162 **********************************/
164 /*#define CONFIG_CLK_667_133_66*/
165 #define CONFIG_CLK_533_133_66
167 #define CONFIG_CLK_400_100_50
168 #define CONFIG_CLK_400_133_66
169 #define CONFIG_SYNC_MODE
172 /* SMDK6400 has 2 banks of DRAM, but we use only one in U-Boot */
173 #define CONFIG_NR_DRAM_BANKS 1
174 #define PHYS_SDRAM_1 CFG_SDRAM_BASE /* SDRAM Bank #1 */
175 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB in Bank #1 */
177 #define CFG_FLASH_BASE 0x10000000
178 #define CFG_MONITOR_BASE 0x00000000
180 /*-----------------------------------------------------------------------
181 * FLASH and environment organization
183 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
184 /* AM29LV160B has 35 sectors, AM29LV800B - 19 */
185 #define CFG_MAX_FLASH_SECT 40
187 #define CONFIG_AMD_LV800
188 #define CFG_FLASH_CFI 1 /* Use CFI parameters (needed?) */
189 /* Use drivers/cfi_flash.c, even though the flash is not CFI-compliant */
190 #define CFG_FLASH_CFI_DRIVER 1
191 #define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
192 #define CONFIG_FLASH_CFI_LEGACY
193 #define CFG_FLASH_LEGACY_512Kx16
195 /* timeout values are in ticks */
196 #define CFG_FLASH_ERASE_TOUT (5 * CFG_HZ) /* Timeout for Flash Erase */
197 #define CFG_FLASH_WRITE_TOUT (5 * CFG_HZ) /* Timeout for Flash Write */
199 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
202 * SMDK6400 board specific data
205 #define CONFIG_IDENT_STRING " for SMDK6400"
207 /* base address for uboot */
208 #define CFG_PHY_UBOOT_BASE (CFG_SDRAM_BASE + 0x07e00000)
209 /* total memory available to uboot */
210 #define CFG_UBOOT_SIZE (1024 * 1024)
212 #ifdef CONFIG_ENABLE_MMU
213 #define CFG_MAPPED_RAM_BASE 0xc0000000
214 #define CONFIG_BOOTCOMMAND "nand read 0xc0018000 0x60000 0x1c0000;" \
217 #define CFG_MAPPED_RAM_BASE CFG_SDRAM_BASE
218 #define CONFIG_BOOTCOMMAND "nand read 0x50018000 0x60000 0x1c0000;" \
222 /* NAND U-Boot load and start address */
223 #define CFG_UBOOT_BASE (CFG_MAPPED_RAM_BASE + 0x07e00000)
225 #define CFG_ENV_OFFSET 0x0040000
227 /* NAND configuration */
228 #define CFG_MAX_NAND_DEVICE 1
229 #define CFG_NAND_BASE 0x70200010
230 #define NAND_MAX_CHIPS 1
231 #define CFG_S3C_NAND_HWECC
233 #define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
234 #define CFG_NAND_WP 1
235 #define CFG_NAND_YAFFS_WRITE 1 /* support yaffs write */
236 #define CFG_NAND_BBT_2NDPAGE 1 /* bad-block markers in 1st and 2nd pages */
238 #define CFG_NAND_U_BOOT_DST CFG_PHY_UBOOT_BASE /* NUB load-addr */
239 #define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* NUB start-addr */
241 #define CFG_NAND_U_BOOT_OFFS (4 * 1024) /* Offset to RAM U-Boot image */
242 #define CFG_NAND_U_BOOT_SIZE (252 * 1024) /* Size of RAM U-Boot image */
244 /* NAND chip page size */
245 #define CFG_NAND_PAGE_SIZE 2048
246 /* NAND chip block size */
247 #define CFG_NAND_BLOCK_SIZE (128 * 1024)
248 /* NAND chip page per block count */
249 #define CFG_NAND_PAGE_COUNT 64
250 /* Location of the bad-block label */
251 #define CFG_NAND_BAD_BLOCK_POS 0
252 /* Extra address cycle for > 128MiB */
253 #define CFG_NAND_5_ADDR_CYCLE
255 /* Size of the block protected by one OOB (Spare Area in Samsung terminology) */
256 #define CFG_NAND_ECCSIZE CFG_NAND_PAGE_SIZE
257 /* Number of ECC bytes per OOB - S3C6400 calculates 4 bytes ECC in 1-bit mode */
258 #define CFG_NAND_ECCBYTES 4
259 /* Number of ECC-blocks per NAND page */
260 #define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
261 /* Size of a single OOB region */
262 #define CFG_NAND_OOBSIZE 64
263 /* Number of ECC bytes per page */
264 #define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
265 /* ECC byte positions */
266 #define CFG_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \
267 48, 49, 50, 51, 52, 53, 54, 55, \
268 56, 57, 58, 59, 60, 61, 62, 63}
270 /* Boot configuration (define only one of next 3) */
271 #define CONFIG_BOOT_NAND
272 /* None of these are currently implemented. Left from the original Samsung
273 * version for reference
274 #define CONFIG_BOOT_NOR
275 #define CONFIG_BOOT_MOVINAND
276 #define CONFIG_BOOT_ONENAND
280 #define CONFIG_NAND_S3C64XX
281 /* Unimplemented or unsupported. See comment above.
282 #define CONFIG_ONENAND
283 #define CONFIG_MOVINAND
286 /* Settings as above boot configuration */
287 #define CFG_ENV_IS_IN_NAND
288 #define CONFIG_BOOTARGS "console=ttySAC,115200"
289 #define CONFIG_EXTRA_ENV_SETTINGS "bootargs=" CONFIG_BOOTARGS
291 #if !defined(CONFIG_ENABLE_MMU)
292 #define CONFIG_CMD_USB 1
293 #define CONFIG_USB_OHCI_NEW 1
294 #define CFG_USB_OHCI_REGS_BASE 0x74300000
295 #define CFG_USB_OHCI_SLOT_NAME "s3c6400"
296 #define CFG_USB_OHCI_MAX_ROOT_PORTS 3
297 #define CFG_USB_OHCI_CPU_INIT 1
298 #define LITTLEENDIAN 1 /* used by usb_ohci.c */
300 #define CONFIG_USB_STORAGE 1
302 #define CONFIG_DOS_PARTITION 1
304 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_ENABLE_MMU)
305 # error "usb_ohci.c is currently broken with MMU enabled."
308 #endif /* __CONFIG_H */