2 * (C) Copyright 2006-2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
6 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
7 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 /************************************************************************
26 * sequoia.h - configuration for Sequoia & Rainier boards
27 ***********************************************************************/
31 /*-----------------------------------------------------------------------
32 * High Level Configuration Options
33 *----------------------------------------------------------------------*/
34 /* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */
35 #ifndef CONFIG_RAINIER
36 #define CONFIG_440EPX 1 /* Specific PPC440EPx */
38 #define CONFIG_440GRX 1 /* Specific PPC440GRx */
40 #define CONFIG_4xx 1 /* ... PPC4xx family */
41 /* Detect Sequoia PLL input clock automatically via CPLD bit */
42 #define CONFIG_SYS_CLK_FREQ ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
45 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
46 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
48 /*-----------------------------------------------------------------------
49 * Base addresses -- Note these are effective addresses where the
50 * actual resources get mapped (not physical addresses)
51 *----------------------------------------------------------------------*/
52 #define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
53 #define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
55 #define CFG_BOOT_BASE_ADDR 0xf0000000
56 #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
57 #define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
58 #define CFG_MONITOR_BASE TEXT_BASE
59 #define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */
60 #define CFG_OCM_BASE 0xe0010000 /* ocm */
61 #define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
62 #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
63 #define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
64 #define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
65 #define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
67 /* Don't change either of these */
68 #define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
70 #define CFG_USB2D0_BASE 0xe0000100
71 #define CFG_USB_DEVICE 0xe0000000
72 #define CFG_USB_HOST 0xe0000400
73 #define CFG_BCSR_BASE 0xc0000000
75 /*-----------------------------------------------------------------------
76 * Initial RAM & stack pointer
77 *----------------------------------------------------------------------*/
78 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
79 #define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
80 #define CFG_INIT_RAM_END (4 << 10)
81 #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
82 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
83 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
85 /*-----------------------------------------------------------------------
87 *----------------------------------------------------------------------*/
88 #define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
89 #define CONFIG_BAUDRATE 115200
90 #define CONFIG_SERIAL_MULTI 1
91 /* define this if you want console on UART1 */
92 #undef CONFIG_UART1_CONSOLE
94 #define CFG_BAUDRATE_TABLE \
95 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
97 /*-----------------------------------------------------------------------
99 *----------------------------------------------------------------------*/
100 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
101 #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
103 #define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
104 #define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
107 /*-----------------------------------------------------------------------
109 *----------------------------------------------------------------------*/
110 #define CFG_FLASH_CFI /* The flash is CFI compatible */
111 #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
113 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
115 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
116 #define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
118 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
119 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
121 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
122 #define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
124 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
125 #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
127 #ifdef CFG_ENV_IS_IN_FLASH
128 #define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
129 #define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
130 #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
132 /* Address and size of Redundant Environment Sector */
133 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
134 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
138 * IPL (Initial Program Loader, integrated inside CPU)
139 * Will load first 4k from NAND (SPL) into cache and execute it from there.
141 * SPL (Secondary Program Loader)
142 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
143 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
144 * controller and the NAND controller so that the special U-Boot image can be
145 * loaded from NAND to SDRAM.
148 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
149 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
151 * On 440EPx the SPL is copied to SDRAM before the NAND controller is
152 * set up. While still running from cache, I experienced problems accessing
153 * the NAND controller. sr - 2006-08-25
155 #define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
156 #define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
157 #define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */
158 #define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
159 #define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
160 #define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
163 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
165 #define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
166 #define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
169 * Now the NAND chip has to be defined (no autodetection used!)
171 #define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
172 #define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
173 #define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
174 #define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
175 #undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
177 #define CFG_NAND_ECCSIZE 256
178 #define CFG_NAND_ECCBYTES 3
179 #define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
180 #define CFG_NAND_OOBSIZE 16
181 #define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
182 #define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
184 #ifdef CFG_ENV_IS_IN_NAND
186 * For NAND booting the environment is embedded in the U-Boot image. Please take
187 * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
189 #define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE
190 #define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
191 #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
194 /*-----------------------------------------------------------------------
196 *----------------------------------------------------------------------*/
197 #define CFG_MBYTES_SDRAM (256) /* 256MB */
198 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
199 #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
202 /*-----------------------------------------------------------------------
204 *----------------------------------------------------------------------*/
205 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
206 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
207 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
208 #define CFG_I2C_SLAVE 0x7F
210 #define CFG_I2C_MULTI_EEPROMS
211 #define CFG_I2C_EEPROM_ADDR (0xa8>>1)
212 #define CFG_I2C_EEPROM_ADDR_LEN 1
213 #define CFG_EEPROM_PAGE_WRITE_ENABLE
214 #define CFG_EEPROM_PAGE_WRITE_BITS 3
215 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
217 /* I2C SYSMON (LM75, AD7414 is almost compatible) */
218 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
219 #define CONFIG_DTT_AD7414 1 /* use AD7414 */
220 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
221 #define CFG_DTT_MAX_TEMP 70
222 #define CFG_DTT_LOW_TEMP -30
223 #define CFG_DTT_HYSTERESIS 3
225 #define CONFIG_PREBOOT "echo;" \
226 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
229 #undef CONFIG_BOOTARGS
231 /* Setup some board specific values for the default environment variables */
232 #ifndef CONFIG_RAINIER
233 #define CONFIG_HOSTNAME sequoia
234 #define CFG_BOOTFILE "bootfile=/tftpboot/sequoia/uImage\0"
235 #define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
237 #define CONFIG_HOSTNAME rainier
238 #define CFG_BOOTFILE "bootfile=/tftpboot/rainier/uImage\0"
239 #define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0"
242 #define CONFIG_EXTRA_ENV_SETTINGS \
246 "nfsargs=setenv bootargs root=/dev/nfs rw " \
247 "nfsroot=${serverip}:${rootpath}\0" \
248 "ramargs=setenv bootargs root=/dev/ram rw\0" \
249 "addip=setenv bootargs ${bootargs} " \
250 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
251 ":${hostname}:${netdev}:off panic=1\0" \
252 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
253 "flash_nfs=run nfsargs addip addtty;" \
254 "bootm ${kernel_addr}\0" \
255 "flash_self=run ramargs addip addtty;" \
256 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
257 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
259 "kernel_addr=FC000000\0" \
260 "ramdisk_addr=FC180000\0" \
261 "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
262 "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
263 "cp.b 200000 FFFA0000 60000\0" \
264 "upd=run load;run update\0" \
266 #define CONFIG_BOOTCOMMAND "run flash_self"
269 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
271 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
274 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
275 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
277 #define CONFIG_M88E1111_PHY 1
278 #define CONFIG_IBM_EMAC4_V4 1
279 #define CONFIG_MII 1 /* MII PHY management */
280 #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
282 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
283 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
285 #define CONFIG_HAS_ETH0
286 #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
288 #define CONFIG_NET_MULTI 1
289 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
290 #define CONFIG_PHY1_ADDR 1
294 #define CONFIG_USB_OHCI
295 #define CONFIG_USB_STORAGE
297 /* Comment this out to enable USB 1.1 device */
298 #define USB_2_0_DEVICE
300 #define CMD_USB CFG_CMD_USB
302 #define CMD_USB 0 /* no USB on 440GRx */
303 #endif /* CONFIG_440EPX */
306 #define CONFIG_MAC_PARTITION
307 #define CONFIG_DOS_PARTITION
308 #define CONFIG_ISO_PARTITION
310 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
330 #define CONFIG_SUPPORT_VFAT
332 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
333 #include <cmd_confdefs.h>
335 /*-----------------------------------------------------------------------
336 * Miscellaneous configurable options
337 *----------------------------------------------------------------------*/
338 #define CFG_LONGHELP /* undef to save memory */
339 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
340 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
341 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
343 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
345 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
346 #define CFG_MAXARGS 16 /* max number of command args */
347 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
349 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
350 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
352 #define CFG_LOAD_ADDR 0x100000 /* default load address */
353 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
355 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
357 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
358 #define CONFIG_LOOPW 1 /* enable loopw command */
359 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
360 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
361 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
363 /*-----------------------------------------------------------------------
365 *----------------------------------------------------------------------*/
367 #define CONFIG_PCI /* include pci support */
368 #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
369 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
370 #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
372 /* Board-specific PCI */
373 #define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
374 #define CFG_PCI_TARGET_INIT
375 #define CFG_PCI_MASTER_INIT
377 #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
378 #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
381 * For booting Linux, the board info and command line data
382 * have to be in the first 8 MB of memory, since this is
383 * the maximum mapped by the Linux kernel during initialization.
385 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
387 /*-----------------------------------------------------------------------
388 * External Bus Controller (EBC) Setup
389 *----------------------------------------------------------------------*/
392 * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
394 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
395 #define CFG_NAND_CS 3 /* NAND chip connected to CSx */
396 /* Memory Bank 0 (NOR-FLASH) initialization */
397 #define CFG_EBC_PB0AP 0x03017200
398 #define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000)
400 /* Memory Bank 3 (NAND-FLASH) initialization */
401 #define CFG_EBC_PB3AP 0x018003c0
402 #define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000)
404 #define CFG_NAND_CS 0 /* NAND chip connected to CSx */
405 /* Memory Bank 3 (NOR-FLASH) initialization */
406 #define CFG_EBC_PB3AP 0x03017200
407 #define CFG_EBC_PB3CR (CFG_FLASH_BASE | 0xda000)
409 /* Memory Bank 0 (NAND-FLASH) initialization */
410 #define CFG_EBC_PB0AP 0x018003c0
411 #define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000)
414 /* Memory Bank 2 (CPLD) initialization */
415 #define CFG_EBC_PB2AP 0x24814580
416 #define CFG_EBC_PB2CR (CFG_BCSR_BASE | 0x38000)
418 /*-----------------------------------------------------------------------
420 *----------------------------------------------------------------------*/
421 #define CFG_MAX_NAND_DEVICE 1
422 #define NAND_MAX_CHIPS 1
423 #define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
424 #define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
426 /*-----------------------------------------------------------------------
427 * Cache Configuration
428 *----------------------------------------------------------------------*/
429 #define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
430 #define CFG_CACHELINE_SIZE 32 /* ... */
431 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
432 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
436 * Internal Definitions
440 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
441 #define BOOTFLAG_WARM 0x02 /* Software reboot */
443 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
444 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
445 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
447 #endif /* __CONFIG_H */