3 * Heiko Schocher, DENX Software Engineering, <hs@denx.de>.
7 * Juergen Beisert, EuroDesign embedded technologies, jbeisert@eurodsn.de
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #undef USE_VGA_GRAPHICS
34 * 0x00000000 .... 0x03FFFFFF -> RAM (up to 128MiB)
35 * 0x74000000 .... 0x740FFFFF -> CS#6
36 * 0x74100000 .... 0x741FFFFF -> CS#7
37 * 0x74200000 .... 0x742FFFFF -> CS4# if no internal USB
38 * 0x74300000 .... 0x743FFFFF -> CS5# if no boosted IDE
39 * 0x77C00000 .... 0x77CFFFFF -> CS4# USB HC (1 MiB)
40 * 0x77D00000 .... 0x77DFFFFF -> CS1# NAND-Flash (1 MiB)
41 * 0x78000000 .... 0x78FFFFFF -> CS2# ISA-Bus Speicherzugriff (16 MiB)
42 * 0x79000000 .... 0x7900FFFF -> CS2# ISA-Bus IO-Zugriff (16 MiB, mapped: 64kiB)
43 * 0x79010000 .... 0x79FFFFFF -> CS2# ISA-Bus IO-Zugriff (mirrored)
44 * 0x7A000000 .... 0x7A0FFFFF -> CS5# IDE emulation (1MiB)
46 * 0x80000000 .... 0x9FFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 1:1)
47 * 0xA0000000 .... 0xBFFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 0x00000000...0x1FFFFFFF)
48 * 0xE8000000 .... 0xE800FFFF -> PCI-Bus IO-Zugriff (64kiB, translated to PCI: 0x0000...0xFFFF)
49 * 0xE8800000 .... 0xEBFFFFFF -> PCI-Bus IO-Zugriff (56MiB, translated to PCI: 0x00800000...0x3FFFFFF)
50 * 0xEED00000 .... 0xEED00003 -> PCI-Bus
51 * 0xEF400000 .... 0xEF40003F -> PCI-Bus Local Configuration Registers
52 * 0xEF40003F .... 0xEF5FFFFF -> reserved
53 * 0xEF600000 .... 0xEFFFFFFF -> 405GP internal Devices (10 MiB)
54 * 0xF0000000 .... 0xF01FFFFF -> Flash-ROM (2 MiB)
55 * 0xF0200000 .... 0xF7FFFFFF -> free for flash devices
56 * 0xF8000000 .... 0xF8000FFF -> OnChipMemory (4kiB)
57 * 0xF8001000 .... 0xFFDFFFFF -> free for flash devices
58 * 0xFFE00000 .... 0xFFFFFFFF -> BOOT-ROM (2 MiB)
61 #define CONFIG_SOLIDCARD3 1
63 #define CONFIG_405GP 1
65 #define CONFIG_BOARD_EARLY_INIT_F 1
68 * Define IDE_USES_ISA_EMULATION for slower IDE access in the ISA-IO address range
69 * If undefined, IDE access uses a seperat emulation with higher access speed.
70 * Consider to inform your Linux IDE driver about the different addresses!
71 * IDE_USES_ISA_EMULATION is only used if your CONFIG_COMMANDS macro includes
72 * the CFG_CMD_IDE macro!
74 #define IDE_USES_ISA_EMULATION
76 /*-----------------------------------------------------------------------
78 *----------------------------------------------------------------------*/
79 #define CONFIG_SERIAL_MULTI
80 #undef CONFIG_SERIAL_SOFTWARE_FIFO
82 * define CONFIG_POWER_DOWN if your cpu should power down while waiting for your input
83 * Works only, if you have enabled the CONFIG_SERIAL_SOFTWARE_FIFO feature
85 #if CONFIG_SERIAL_SOFTWARE_FIFO
86 #define CONFIG_POWER_DOWN
90 * define CONFIG_SYS_CLK_FREQ to your base crystal clock in Hz
92 #define CONFIG_SYS_CLK_FREQ 33333333
95 * define CONFIG_BAUDRATE to the baudrate value you want to use as default
97 #define CONFIG_BAUDRATE 115200
98 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
100 #define CONFIG_PREBOOT "echo;" \
101 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
104 #undef CONFIG_BOOTARGS
106 #define CONFIG_EXTRA_ENV_SETTINGS \
108 "nfsargs=setenv bootargs root=/dev/nfs rw " \
109 "nfsroot=${serverip}:${rootpath}\0" \
110 "ramargs=setenv bootargs root=/dev/ram rw\0" \
111 "nand_args=setenv bootargs root=/dev/mtdblock4 rw\0" \
112 "addip=setenv bootargs ${bootargs} " \
113 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
114 ":${hostname}:${netdev}:off panic=1\0" \
115 "flash_nfs=run nfsargs addip;" \
116 "bootm ${kernel_addr}\0" \
117 "flash_nand=nand_args addip addcon;bootm ${kernel_addr}\0" \
118 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
119 "rootpath=/opt/eldk/ppc_4xx\0" \
120 "bootfile=/tftpboot/sc3/uImage\0" \
121 "kernel_addr=FFE08000\0" \
123 #undef CONFIG_BOOTCOMMAND
125 #define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
126 #define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
128 #if 1 /* feel free to disable for development */
129 #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
130 #define CONFIG_AUTOBOOT_PROMPT "\nSC3 - booting... stop with S\n"
131 #define CONFIG_AUTOBOOT_DELAY_STR "S" /* 1st "password" */
135 * define CONFIG_BOOTCOMMAND to the autoboot commands. They will running after
136 * the CONFIG_BOOTDELAY delay to boot your machine
138 #define CONFIG_BOOTCOMMAND "bootp;dcache on;bootm"
141 * define CONFIG_BOOTARGS to the default kernel parameters. They will used if you don't
142 * set different values at the u-boot prompt
144 #ifdef USE_VGA_GRAPHICS
145 #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp nfsroot=/tftpboot/solidcard3re"
147 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/nfs rw ip=bootp"
150 * Is the USB host controller assembled? If yes define CONFIG_ISP1161_PRESENT
151 * This reserves memory bank #4 for this purpose
153 #undef CONFIG_ISP1161_PRESENT
155 #undef CONFIG_LOADS_ECHO /* no echo on for serial download */
156 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
158 #define CONFIG_NET_MULTI
159 /* #define CONFIG_EEPRO100_SROM_WRITE */
160 /* #define CONFIG_SHOW_MAC */
161 #define CONFIG_EEPRO100
162 #define CONFIG_MII 1 /* add 405GP MII PHY management */
163 #define CONFIG_PHY_ADDR 1 /* the connected Phy defaults to address 1 */
165 #define CONFIG_COMMANDS \
180 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
181 #include <cmd_confdefs.h>
183 #undef CONFIG_WATCHDOG /* watchdog disabled */
186 * Miscellaneous configurable options
188 #define CFG_LONGHELP 1 /* undef to save memory */
189 #define CFG_PROMPT "SC3> " /* Monitor Command Prompt */
190 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
192 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
194 #define CFG_MAXARGS 16 /* max number of command args */
195 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
197 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
198 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
201 * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
202 * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
203 * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
204 * The Linux BASE_BAUD define should match this configuration.
205 * baseBaud = cpuClock/(uartDivisor*16)
206 * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
207 * set Linux BASE_BAUD to 403200.
209 * Consider the OPB clock! If it get lower the BASE_BAUD must be lower to
210 * (see 405GP datasheet for descritpion)
212 #undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
213 #undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
214 #define CFG_BASE_BAUD 921600 /* internal clock */
216 /* The following table includes the supported baudrates */
217 #define CFG_BAUDRATE_TABLE \
218 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
220 #define CFG_LOAD_ADDR 0x1000000 /* default load address */
221 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
223 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
225 /*-----------------------------------------------------------------------
227 *-----------------------------------------------------------------------
229 #define CONFIG_HARD_I2C /* I2C with hardware support */
230 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
234 #define I2C_TRISTATE 0
236 #define CFG_I2C_SPEED 100000 /* use the standard 100kHz speed */
237 #define CFG_I2C_SLAVE 0x7F /* mask valid bits */
239 #define CONFIG_RTC_DS1337
240 #define CFG_I2C_RTC_ADDR 0x68
242 /*-----------------------------------------------------------------------
244 *-----------------------------------------------------------------------
246 #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
247 #define PCI_HOST_FORCE 1 /* configure as pci host */
248 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
250 #define CONFIG_PCI /* include pci support */
251 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
252 #define CONFIG_PCI_PNP /* do pci plug-and-play */
253 /* resource configuration */
255 /* If you want to see, whats connected to your PCI bus */
256 /* #define CONFIG_PCI_SCAN_SHOW */
258 #define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
259 #define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
260 #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
261 #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
262 #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
263 #define CFG_PCI_PTM2LA 0x00000000 /* disabled */
264 #define CFG_PCI_PTM2MS 0x00000000 /* disabled */
265 #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
267 /*-----------------------------------------------------------------------
268 * External peripheral base address
269 *-----------------------------------------------------------------------
271 #if !(CONFIG_COMMANDS & CFG_CMD_IDE)
273 #undef CONFIG_IDE_LED /* no led for ide supported */
274 #undef CONFIG_IDE_RESET /* no reset for ide supported */
276 /*-----------------------------------------------------------------------
278 *-----------------------------------------------------------------------
280 #else /* !(CONFIG_COMMANDS & CFG_CMD_IDE) */
281 #define CONFIG_START_IDE 1 /* check, if use IDE */
283 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
284 #undef CONFIG_IDE_LED /* no led for ide supported */
285 #undef CONFIG_IDE_RESET /* no reset for ide supported */
288 #define CONFIG_DOS_PARTITION
289 #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
291 #ifndef IDE_USES_ISA_EMULATION
293 /* New and faster access */
294 #define CFG_ATA_BASE_ADDR 0x7A000000 /* start of ISA IO emulation */
296 /* How many IDE busses are available */
297 #define CFG_IDE_MAXBUS 1
299 /* What IDE ports are available */
300 #define CFG_ATA_IDE0_OFFSET 0x000 /* first is available */
301 #undef CFG_ATA_IDE1_OFFSET /* second not available */
303 /* access to the data port is calculated:
304 CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_DATA_OFFSET + 0 */
305 #define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
307 /* access to the registers is calculated:
308 CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_REG_OFFSET + [1..7] */
309 #define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
311 /* access to the alternate register is calculated:
312 CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_ALT_OFFSET + 6 */
313 #define CFG_ATA_ALT_OFFSET 0x008 /* Offset for alternate registers */
315 #else /* IDE_USES_ISA_EMULATION */
317 #define CFG_ATA_BASE_ADDR 0x79000000 /* start of ISA IO emulation */
319 /* How many IDE busses are available */
320 #define CFG_IDE_MAXBUS 1
322 /* What IDE ports are available */
323 #define CFG_ATA_IDE0_OFFSET 0x01F0 /* first is available */
324 #undef CFG_ATA_IDE1_OFFSET /* second not available */
326 /* access to the data port is calculated:
327 CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_DATA_OFFSET + 0 */
328 #define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
330 /* access to the registers is calculated:
331 CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_REG_OFFSET + [1..7] */
332 #define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
334 /* access to the alternate register is calculated:
335 CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_ALT_OFFSET + 6 */
336 #define CFG_ATA_ALT_OFFSET 0x03F0 /* Offset for alternate registers */
338 #endif /* IDE_USES_ISA_EMULATION */
340 #endif /* !(CONFIG_COMMANDS & CFG_CMD_IDE) */
343 #define CFG_KEY_REG_BASE_ADDR 0xF0100000
344 #define CFG_IR_REG_BASE_ADDR 0xF0200000
345 #define CFG_FPGA_REG_BASE_ADDR 0xF0300000
348 /*-----------------------------------------------------------------------
349 * Start addresses for the final memory configuration
350 * (Set up by the startup code)
351 * Please note that CFG_SDRAM_BASE _must_ start at 0
353 * CFG_FLASH_BASE -> start address of internal flash
354 * CFG_MONITOR_BASE -> start of u-boot
356 #ifndef __ASSEMBLER__
357 extern unsigned long offsetOfBigFlash;
358 extern unsigned long offsetOfEnvironment;
361 #define CFG_SDRAM_BASE 0x00000000
362 #define CFG_FLASH_BASE 0xFFE00000
363 #define CFG_MONITOR_BASE 0xFFFC0000 /* placed last 256k */
364 #define CFG_MONITOR_LEN (224 * 1024) /* Reserve 224 KiB for Monitor */
365 #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 KiB for malloc() */
368 * For booting Linux, the board info and command line data
369 * have to be in the first 8 MiB of memory, since this is
370 * the maximum mapped by the Linux kernel during initialization.
372 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
373 /*-----------------------------------------------------------------------
374 * FLASH organization ## FIXME: lookup in datasheet
376 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
377 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
379 #define CFG_FLASH_CFI /* flash is CFI compat. */
380 #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/
381 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
382 #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
383 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
384 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
386 #define CFG_ENV_IS_IN_FLASH 1
387 #if CFG_ENV_IS_IN_FLASH
388 #define CFG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector in bottom type */
389 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
390 #define CFG_ENV_SECT_SIZE 0x4000 /* see README - env sector total size */
392 /* Address and size of Redundant Environment Sector */
393 #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
394 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
397 /* let us changing anything in our environment */
398 #define CONFIG_ENV_OVERWRITE
403 #define CFG_MAX_NAND_DEVICE 1
404 #define NAND_MAX_CHIPS 1
405 #define CFG_NAND_BASE 0x77D00000
407 /*-----------------------------------------------------------------------
408 * Cache Configuration
410 * CFG_DCACHE_SIZE -> size of data cache:
413 * How to handle the difference in chache size?
414 * CFG_CACHELINE_SIZE -> size of one cache line: 32 bytes
415 * (used in cpu/ppc4xx/start.S)
417 #define CFG_DCACHE_SIZE 16384
419 #define CFG_CACHELINE_SIZE 32
421 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
422 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
426 * Init Memory Controller:
430 #define FLASH_BASE0_PRELIM CFG_FLASH_BASE
431 #define FLASH_BASE1_PRELIM 0
433 /*-----------------------------------------------------------------------
434 * Some informations about the internal SRAM (OCM=On Chip Memory)
436 * CFG_OCM_DATA_ADDR -> location
437 * CFG_OCM_DATA_SIZE -> size
440 #define CFG_TEMP_STACK_OCM 1
441 #define CFG_OCM_DATA_ADDR 0xF8000000
442 #define CFG_OCM_DATA_SIZE 0x1000
444 /*-----------------------------------------------------------------------
445 * Definitions for initial stack pointer and data area (in DPRAM):
446 * - we are using the internal 4k SRAM, so we don't need data cache mapping
447 * - internal SRAM (OCM=On Chip Memory) is placed to CFG_OCM_DATA_ADDR
448 * - Stackpointer will be located to
449 * (CFG_INIT_RAM_ADDR&0xFFFF0000) | (CFG_INIT_SP_OFFSET&0x0000FFFF)
450 * in cpu/ppc4xx/start.S
453 #undef CFG_INIT_DCACHE_CS
454 /* Where the internal SRAM starts */
455 #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR
456 /* Where the internal SRAM ends (only offset) */
457 #define CFG_INIT_RAM_END 0x0F00
461 CFG_INIT_RAM_ADDR ------> ------------ lower address
466 CFG_GBL_DATA_OFFSET ----> ------------
470 CFG_INIT_RAM_END ------> ------------ higher address
474 /* size in bytes reserved for initial data */
475 #define CFG_GBL_DATA_SIZE 64
476 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
477 /* Initial value of the stack pointern in internal SRAM */
478 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
481 * Internal Definitions
485 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
486 #define BOOTFLAG_WARM 0x02 /* Software reboot */
488 /* ################################################################################### */
489 /* These defines will be used in cpu/ppc4xx/cpu_init.c to setup external chip selects */
490 /* They are currently undefined cause they are initiaized in board/solidcard3/init.S */
492 /* This chip select accesses the boot device */
493 /* It depends on boot select switch if this device is 16 or 8 bit */
519 #define CONFIG_SDRAM_BANK0 /* use the standard SDRAM initialization */
520 #undef CONFIG_SPD_EEPROM
523 * Define this to get more information about system configuration
525 /* #define SC3_DEBUGOUT */
528 /***********************************************************************
529 * External peripheral base address
530 ***********************************************************************/
532 #define CFG_ISA_MEM_BASE_ADDRESS 0x78000000
534 Die Grafik-Treiber greifen über die Adresse in diesem Macro auf den Chip zu.
535 Das funktioniert bei deren Karten, weil sie eine PCI-Bridge benutzen, die
536 das gleiche Mapping durchführen kann, wie der SC520 (also Aufteilen von IO-Zugriffen
537 auf ISA- und PCI-Zyklen)
539 #define CFG_ISA_IO_BASE_ADDRESS 0xE8000000
540 /*#define CFG_ISA_IO_BASE_ADDRESS 0x79000000 */
542 /************************************************************
544 ************************************************************/
546 #ifdef USE_VGA_GRAPHICS
547 #define CONFIG_VIDEO /* To enable video controller support */
548 #define CONFIG_VIDEO_CT69000
549 #define CONFIG_CFB_CONSOLE
550 /* #define CONFIG_VIDEO_LOGO */
551 #define CONFIG_VGA_AS_SINGLE_DEVICE
552 #define CONFIG_VIDEO_SW_CURSOR
553 /* #define CONFIG_VIDEO_HW_CURSOR */
554 #define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */
556 #define VIDEO_HW_RECTFILL
557 #define VIDEO_HW_BITBLT
561 /************************************************************
563 ************************************************************/
564 #define CONFIG_SC3_VERSION "r1.4"
566 #define POST_OUT(x) (*((volatile unsigned char*)(0x79000080))=x)
568 #endif /* __CONFIG_H */