include/configs/sbc8349.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * WindRiver SBC8349 U-Boot configuration file.
   4  * Copyright (c) 2006, 2007 Wind River Systems, Inc.
   5  *
   6  * Paul Gortmaker <paul.gortmaker@windriver.com>
   7  * Based on the MPC8349EMDS config.
   8  */
   9
  10 /*
  11  * sbc8349 board configuration file.
  12  */
  13
  14 #ifndef __CONFIG_H
  15 #define __CONFIG_H
  16
  17 /*
  18  * High Level Configuration Options
  19  */
  20 #define CONFIG_E300             1       /* E300 Family */
  21
  22 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
  23 #undef CONFIG_MPC83XX_PCI2              /* support for 2nd PCI controller */
  24
  25 #ifdef CONFIG_PCI_33M
  26 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_8X1
  27 #else   /* 66M */
  28 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_4X1
  29 #endif
  30
  31 #define CONFIG_SYS_IMMR         0xE0000000
  32
  33 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  34 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  35 #define CONFIG_SYS_MEMTEST_END          0x00100000
  36
  37 /*
  38  * DDR Setup
  39  */
  40 #undef CONFIG_DDR_ECC                   /* only for ECC DDR module */
  41 #undef CONFIG_DDR_ECC_CMD               /* use DDR ECC user commands */
  42 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
  43 #define CONFIG_SYS_83XX_DDR_USES_CS0    /* WRS; Fsl board uses CS2/CS3 */
  44
  45 /*
  46  * 32-bit data path mode.
  47  *
  48  * Please note that using this mode for devices with the real density of 64-bit
  49  * effectively reduces the amount of available memory due to the effect of
  50  * wrapping around while translating address to row/columns, for example in the
  51  * 256MB module the upper 128MB get aliased with contents of the lower
  52  * 128MB); normally this define should be used for devices with real 32-bit
  53  * data path.
  54  */
  55 #undef CONFIG_DDR_32BIT
  56
  57 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
  58 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  59 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  60 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  61                                 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  62 #define CONFIG_DDR_2T_TIMING
  63
  64 #if defined(CONFIG_SPD_EEPROM)
  65 /*
  66  * Determine DDR configuration from I2C interface.
  67  */
  68 #define SPD_EEPROM_ADDRESS      0x52            /* DDR DIMM */
  69
  70 #else
  71 /*
  72  * Manually set up DDR parameters
  73  * NB: manual DDR setup untested on sbc834x
  74  */
  75 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
  76 #define CONFIG_SYS_DDR_CS2_CONFIG       (CSCONFIG_EN \
  77                                         | CSCONFIG_ROW_BIT_13 \
  78                                         | CSCONFIG_COL_BIT_10)
  79 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
  80 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
  81 #define CONFIG_SYS_DDR_CONTROL  0xc2000000      /* unbuffered,no DYN_PWR */
  82 #define CONFIG_SYS_DDR_INTERVAL 0x04060100      /* autocharge,no open page */
  83
  84 #if defined(CONFIG_DDR_32BIT)
  85 /* set burst length to 8 for 32-bit data path */
  86                                 /* DLL,normal,seq,4/2.5, 8 burst len */
  87 #define CONFIG_SYS_DDR_MODE     0x00000023
  88 #else
  89 /* the default burst length is 4 - for 64-bit data path */
  90                                 /* DLL,normal,seq,4/2.5, 4 burst len */
  91 #define CONFIG_SYS_DDR_MODE     0x00000022
  92 #endif
  93 #endif
  94
  95 /*
  96  * SDRAM on the Local Bus
  97  */
  98 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* Localbus SDRAM */
  99 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 100
 101 /*
 102  * FLASH on the Local Bus
 103  */
 104 #define CONFIG_SYS_FLASH_BASE           0xFF800000      /* start of FLASH   */
 105 #define CONFIG_SYS_FLASH_SIZE           8               /* flash size in MB */
 106
 107 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE \
 108                                         | BR_PS_16      /* 16 bit port */ \
 109                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 110                                         | BR_V)         /* valid */
 111
 112 #define CONFIG_SYS_OR0_PRELIM           (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 113                                         | OR_GPCM_XAM \
 114                                         | OR_GPCM_CSNT \
 115                                         | OR_GPCM_ACS_DIV2 \
 116                                         | OR_GPCM_XACS \
 117                                         | OR_GPCM_SCY_15 \
 118                                         | OR_GPCM_TRLX_SET \
 119                                         | OR_GPCM_EHTR_SET \
 120                                         | OR_GPCM_EAD)
 121                                         /* 0xFF806FF7 */
 122
 123                                         /* window base at flash base */
 124 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 125 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
 126
 127 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 128 #define CONFIG_SYS_MAX_FLASH_SECT       64      /* sectors per device */
 129
 130 #undef CONFIG_SYS_FLASH_CHECKSUM
 131 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 132 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 133
 134 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 135
 136 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 137 #define CONFIG_SYS_RAMBOOT
 138 #else
 139 #undef  CONFIG_SYS_RAMBOOT
 140 #endif
 141
 142 #define CONFIG_SYS_INIT_RAM_LOCK        1
 143                                         /* Initial RAM address */
 144 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000
 145                                         /* Size of used area in RAM*/
 146 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000
 147
 148 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 149                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 150 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 151
 152 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024)    /* Reserve 256 kB for Mon */
 153 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 154
 155 /*
 156  * Local Bus LCRR and LBCR regs
 157  *    LCRR:  DLL bypass, Clock divider is 4
 158  * External Local Bus rate is
 159  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 160  */
 161 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 162 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 163 #define CONFIG_SYS_LBC_LBCR     0x00000000
 164
 165 #undef CONFIG_SYS_LB_SDRAM      /* if board has SDRAM on local bus */
 166
 167 #ifdef CONFIG_SYS_LB_SDRAM
 168 /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/
 169 /*
 170  * Base Register 2 and Option Register 2 configure SDRAM.
 171  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 172  *
 173  * For BR2, need:
 174  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 175  *    port-size = 32-bits = BR2[19:20] = 11
 176  *    no parity checking = BR2[21:22] = 00
 177  *    SDRAM for MSEL = BR2[24:26] = 011
 178  *    Valid = BR[31] = 1
 179  *
 180  * 0    4    8    12   16   20   24   28
 181  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
 182  */
 183
 184 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_LBC_SDRAM_BASE \
 185                                         | BR_PS_32 \
 186                                         | BR_MS_SDRAM \
 187                                         | BR_V)
 188                                         /* 0xF0001861 */
 189 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_LBC_SDRAM_BASE
 190 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_64MB)
 191
 192 /*
 193  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 194  *
 195  * For OR2, need:
 196  *    64MB mask for AM, OR2[0:7] = 1111 1100
 197  *                 XAM, OR2[17:18] = 11
 198  *    9 columns OR2[19-21] = 010
 199  *    13 rows   OR2[23-25] = 100
 200  *    EAD set for extra time OR[31] = 1
 201  *
 202  * 0    4    8    12   16   20   24   28
 203  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
 204  */
 205
 206 #define CONFIG_SYS_OR2_PRELIM   (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
 207                         | OR_SDRAM_XAM \
 208                         | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
 209                         | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
 210                         | OR_SDRAM_EAD)
 211                         /* 0xFC006901 */
 212
 213                                 /* LB sdram refresh timer, about 6us */
 214 #define CONFIG_SYS_LBC_LSRT     0x32000000
 215                                 /* LB refresh timer prescal, 266MHz/32 */
 216 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 217
 218 #define CONFIG_SYS_LBC_LSDMR_COMMON     (LSDMR_RFEN \
 219                                         | LSDMR_BSMA1516 \
 220                                         | LSDMR_RFCR8 \
 221                                         | LSDMR_PRETOACT6 \
 222                                         | LSDMR_ACTTORW3 \
 223                                         | LSDMR_BL8 \
 224                                         | LSDMR_WRC3 \
 225                                         | LSDMR_CL3)
 226
 227 /*
 228  * SDRAM Controller configuration sequence.
 229  */
 230 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 231 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 232 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 233 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 234 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 235 #endif
 236
 237 /*
 238  * Serial Port
 239  */
 240 #define CONFIG_SYS_NS16550_SERIAL
 241 #define CONFIG_SYS_NS16550_REG_SIZE    1
 242 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 243
 244 #define CONFIG_SYS_BAUDRATE_TABLE  \
 245                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 246
 247 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 248 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 249
 250 /* I2C */
 251 #define CONFIG_SYS_I2C
 252 #define CONFIG_SYS_I2C_FSL
 253 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 254 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 255 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 256 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 257 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 258 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 259 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69}, {1, 0x69} }
 260 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
 261
 262 /* TSEC */
 263 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 264 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 265 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 266 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 267
 268 /*
 269  * General PCI
 270  * Addresses are mapped 1-1.
 271  */
 272 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 273 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 274 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 275 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 276 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 277 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 278 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 279 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 280 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 281
 282 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 283 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 284 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 285 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 286 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 287 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 288 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 289 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 290 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 291
 292 #if defined(CONFIG_PCI)
 293
 294 #undef CONFIG_EEPRO100
 295 #undef CONFIG_TULIP
 296
 297 #if !defined(CONFIG_PCI_PNP)
 298         #define PCI_ENET0_IOADDR        0xFIXME
 299         #define PCI_ENET0_MEMADDR       0xFIXME
 300         #define PCI_IDSEL_NUMBER        0xFIXME
 301 #endif
 302
 303 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 304 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 305
 306 #endif  /* CONFIG_PCI */
 307
 308 /*
 309  * TSEC configuration
 310  */
 311
 312 #if defined(CONFIG_TSEC_ENET)
 313
 314 #define CONFIG_TSEC1    1
 315 #define CONFIG_TSEC1_NAME       "TSEC0"
 316 #define CONFIG_TSEC2    1
 317 #define CONFIG_TSEC2_NAME       "TSEC1"
 318 #define CONFIG_PHY_BCM5421S     1
 319 #define TSEC1_PHY_ADDR          0x19
 320 #define TSEC2_PHY_ADDR          0x1a
 321 #define TSEC1_PHYIDX            0
 322 #define TSEC2_PHYIDX            0
 323 #define TSEC1_FLAGS             TSEC_GIGABIT
 324 #define TSEC2_FLAGS             TSEC_GIGABIT
 325
 326 /* Options are: TSEC[0-1] */
 327 #define CONFIG_ETHPRIME         "TSEC0"
 328
 329 #endif  /* CONFIG_TSEC_ENET */
 330
 331 /*
 332  * Environment
 333  */
 334 #ifndef CONFIG_SYS_RAMBOOT
 335         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 336         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 337         #define CONFIG_ENV_SIZE         0x2000
 338
 339 /* Address and size of Redundant Environment Sector     */
 340 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 341 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 342
 343 #else
 344         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 345         #define CONFIG_ENV_SIZE         0x2000
 346 #endif
 347
 348 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 349 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 350
 351 /*
 352  * BOOTP options
 353  */
 354 #define CONFIG_BOOTP_BOOTFILESIZE
 355
 356 /*
 357  * Command line configuration.
 358  */
 359
 360 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 361
 362 /*
 363  * Miscellaneous configurable options
 364  */
 365 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 366
 367 /*
 368  * For booting Linux, the board info and command line data
 369  * have to be in the first 256 MB of memory, since this is
 370  * the maximum mapped by the Linux kernel during initialization.
 371  */
 372                                 /* Initial Memory map for Linux*/
 373 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 374
 375 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 376
 377 #if 1 /*528/264*/
 378 #define CONFIG_SYS_HRCW_LOW (\
 379         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 380         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 381         HRCWL_CSB_TO_CLKIN |\
 382         HRCWL_VCO_1X2 |\
 383         HRCWL_CORE_TO_CSB_2X1)
 384 #elif 0 /*396/132*/
 385 #define CONFIG_SYS_HRCW_LOW (\
 386         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 387         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 388         HRCWL_CSB_TO_CLKIN |\
 389         HRCWL_VCO_1X4 |\
 390         HRCWL_CORE_TO_CSB_3X1)
 391 #elif 0 /*264/132*/
 392 #define CONFIG_SYS_HRCW_LOW (\
 393         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 394         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 395         HRCWL_CSB_TO_CLKIN |\
 396         HRCWL_VCO_1X4 |\
 397         HRCWL_CORE_TO_CSB_2X1)
 398 #elif 0 /*132/132*/
 399 #define CONFIG_SYS_HRCW_LOW (\
 400         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 401         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 402         HRCWL_CSB_TO_CLKIN |\
 403         HRCWL_VCO_1X4 |\
 404         HRCWL_CORE_TO_CSB_1X1)
 405 #elif 0 /*264/264 */
 406 #define CONFIG_SYS_HRCW_LOW (\
 407         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 408         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 409         HRCWL_CSB_TO_CLKIN |\
 410         HRCWL_VCO_1X4 |\
 411         HRCWL_CORE_TO_CSB_1X1)
 412 #endif
 413
 414 #if defined(CONFIG_PCI_64BIT)
 415 #define CONFIG_SYS_HRCW_HIGH (\
 416         HRCWH_PCI_HOST |\
 417         HRCWH_64_BIT_PCI |\
 418         HRCWH_PCI1_ARBITER_ENABLE |\
 419         HRCWH_PCI2_ARBITER_DISABLE |\
 420         HRCWH_CORE_ENABLE |\
 421         HRCWH_FROM_0X00000100 |\
 422         HRCWH_BOOTSEQ_DISABLE |\
 423         HRCWH_SW_WATCHDOG_DISABLE |\
 424         HRCWH_ROM_LOC_LOCAL_16BIT |\
 425         HRCWH_TSEC1M_IN_GMII |\
 426         HRCWH_TSEC2M_IN_GMII)
 427 #else
 428 #define CONFIG_SYS_HRCW_HIGH (\
 429         HRCWH_PCI_HOST |\
 430         HRCWH_32_BIT_PCI |\
 431         HRCWH_PCI1_ARBITER_ENABLE |\
 432         HRCWH_PCI2_ARBITER_ENABLE |\
 433         HRCWH_CORE_ENABLE |\
 434         HRCWH_FROM_0X00000100 |\
 435         HRCWH_BOOTSEQ_DISABLE |\
 436         HRCWH_SW_WATCHDOG_DISABLE |\
 437         HRCWH_ROM_LOC_LOCAL_16BIT |\
 438         HRCWH_TSEC1M_IN_GMII |\
 439         HRCWH_TSEC2M_IN_GMII)
 440 #endif
 441
 442 /* System IO Config */
 443 #define CONFIG_SYS_SICRH 0
 444 #define CONFIG_SYS_SICRL SICRL_LDP_A
 445
 446 #define CONFIG_SYS_HID0_INIT    0x000000000
 447 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK \
 448                                 | HID0_ENABLE_INSTRUCTION_CACHE)
 449
 450 /* #define CONFIG_SYS_HID0_FINAL        (\
 451         HID0_ENABLE_INSTRUCTION_CACHE |\
 452         HID0_ENABLE_M_BIT |\
 453         HID0_ENABLE_ADDRESS_BROADCAST) */
 454
 455 #define CONFIG_SYS_HID2 HID2_HBE
 456
 457 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 458
 459 /* DDR @ 0x00000000 */
 460 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 461                                 | BATL_PP_RW \
 462                                 | BATL_MEMCOHERENCE)
 463 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 464                                 | BATU_BL_256M \
 465                                 | BATU_VS \
 466                                 | BATU_VP)
 467
 468 /* PCI @ 0x80000000 */
 469 #ifdef CONFIG_PCI
 470 #define CONFIG_PCI_INDIRECT_BRIDGE
 471 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE \
 472                                 | BATL_PP_RW \
 473                                 | BATL_MEMCOHERENCE)
 474 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 475                                 | BATU_BL_256M \
 476                                 | BATU_VS \
 477                                 | BATU_VP)
 478 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 479                                 | BATL_PP_RW \
 480                                 | BATL_CACHEINHIBIT \
 481                                 | BATL_GUARDEDSTORAGE)
 482 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 483                                 | BATU_BL_256M \
 484                                 | BATU_VS \
 485                                 | BATU_VP)
 486 #else
 487 #define CONFIG_SYS_IBAT1L       (0)
 488 #define CONFIG_SYS_IBAT1U       (0)
 489 #define CONFIG_SYS_IBAT2L       (0)
 490 #define CONFIG_SYS_IBAT2U       (0)
 491 #endif
 492
 493 #ifdef CONFIG_MPC83XX_PCI2
 494 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE \
 495                                 | BATL_PP_RW \
 496                                 | BATL_MEMCOHERENCE)
 497 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE \
 498                                 | BATU_BL_256M \
 499                                 | BATU_VS \
 500                                 | BATU_VP)
 501 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE \
 502                                 | BATL_PP_RW \
 503                                 | BATL_CACHEINHIBIT \
 504                                 | BATL_GUARDEDSTORAGE)
 505 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE \
 506                                 | BATU_BL_256M \
 507                                 | BATU_VS \
 508                                 | BATU_VP)
 509 #else
 510 #define CONFIG_SYS_IBAT3L       (0)
 511 #define CONFIG_SYS_IBAT3U       (0)
 512 #define CONFIG_SYS_IBAT4L       (0)
 513 #define CONFIG_SYS_IBAT4U       (0)
 514 #endif
 515
 516 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
 517 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 518                                 | BATL_PP_RW \
 519                                 | BATL_CACHEINHIBIT \
 520                                 | BATL_GUARDEDSTORAGE)
 521 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 522                                 | BATU_BL_256M \
 523                                 | BATU_VS \
 524                                 | BATU_VP)
 525
 526 /* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 527 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_LBC_SDRAM_BASE \
 528                                 | BATL_PP_RW \
 529                                 | BATL_MEMCOHERENCE \
 530                                 | BATL_GUARDEDSTORAGE)
 531 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_LBC_SDRAM_BASE \
 532                                 | BATU_BL_256M \
 533                                 | BATU_VS \
 534                                 | BATU_VP)
 535
 536 #define CONFIG_SYS_IBAT7L       (0)
 537 #define CONFIG_SYS_IBAT7U       (0)
 538
 539 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 540 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 541 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 542 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 543 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 544 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 545 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 546 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 547 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 548 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 549 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 550 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 551 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 552 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 553 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 554 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 555
 556 #if defined(CONFIG_CMD_KGDB)
 557 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 558 #endif
 559
 560 /*
 561  * Environment Configuration
 562  */
 563 #define CONFIG_ENV_OVERWRITE
 564
 565 #if defined(CONFIG_TSEC_ENET)
 566 #define CONFIG_HAS_ETH0
 567 #define CONFIG_HAS_ETH1
 568 #endif
 569
 570 #define CONFIG_HOSTNAME         "SBC8349"
 571 #define CONFIG_ROOTPATH         "/tftpboot/rootfs"
 572 #define CONFIG_BOOTFILE         "uImage"
 573
 574                                 /* default location for tftp and bootm */
 575 #define CONFIG_LOADADDR         800000
 576
 577 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 578         "netdev=eth0\0"                                                 \
 579         "hostname=sbc8349\0"                                            \
 580         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 581                 "nfsroot=${serverip}:${rootpath}\0"                     \
 582         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 583         "addip=setenv bootargs ${bootargs} "                            \
 584                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 585                 ":${hostname}:${netdev}:off panic=1\0"                  \
 586         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 587         "flash_nfs=run nfsargs addip addtty;"                           \
 588                 "bootm ${kernel_addr}\0"                                \
 589         "flash_self=run ramargs addip addtty;"                          \
 590                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 591         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 592                 "bootm\0"                                               \
 593         "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0"               \
 594         "update=protect off ff800000 ff83ffff; "                        \
 595                 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
 596         "upd=run load update\0"                                         \
 597         "fdtaddr=780000\0"                                              \
 598         "fdtfile=sbc8349.dtb\0"                                         \
 599         ""
 600
 601 #define CONFIG_NFSBOOTCOMMAND                                           \
 602         "setenv bootargs root=/dev/nfs rw "                             \
 603                 "nfsroot=$serverip:$rootpath "                          \
 604                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 605                                                         "$netdev:off "  \
 606                 "console=$consoledev,$baudrate $othbootargs;"           \
 607         "tftp $loadaddr $bootfile;"                                     \
 608         "tftp $fdtaddr $fdtfile;"                                       \
 609         "bootm $loadaddr - $fdtaddr"
 610
 611 #define CONFIG_RAMBOOTCOMMAND                                           \
 612         "setenv bootargs root=/dev/ram rw "                             \
 613                 "console=$consoledev,$baudrate $othbootargs;"           \
 614         "tftp $ramdiskaddr $ramdiskfile;"                               \
 615         "tftp $loadaddr $bootfile;"                                     \
 616         "tftp $fdtaddr $fdtfile;"                                       \
 617         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 618
 619 #define CONFIG_BOOTCOMMAND      "run flash_self"
 620
 621 #endif  /* __CONFIG_H */