1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * WindRiver SBC8349 U-Boot configuration file.
4 * Copyright (c) 2006, 2007 Wind River Systems, Inc.
6 * Paul Gortmaker <paul.gortmaker@windriver.com>
7 * Based on the MPC8349EMDS config.
11 * sbc8349 board configuration file.
18 * High Level Configuration Options
20 #define CONFIG_E300 1 /* E300 Family */
22 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
23 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
25 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
26 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
27 #define CONFIG_SYS_MEMTEST_END 0x00100000
32 #undef CONFIG_DDR_ECC /* only for ECC DDR module */
33 #undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
34 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
35 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */
38 * 32-bit data path mode.
40 * Please note that using this mode for devices with the real density of 64-bit
41 * effectively reduces the amount of available memory due to the effect of
42 * wrapping around while translating address to row/columns, for example in the
43 * 256MB module the upper 128MB get aliased with contents of the lower
44 * 128MB); normally this define should be used for devices with real 32-bit
47 #undef CONFIG_DDR_32BIT
49 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
50 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
51 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
52 #define CONFIG_DDR_2T_TIMING
54 #if defined(CONFIG_SPD_EEPROM)
56 * Determine DDR configuration from I2C interface.
58 #define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */
62 * Manually set up DDR parameters
63 * NB: manual DDR setup untested on sbc834x
65 #define CONFIG_SYS_DDR_SIZE 256 /* MB */
66 #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
67 | CSCONFIG_ROW_BIT_13 \
68 | CSCONFIG_COL_BIT_10)
69 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
70 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
71 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
72 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
74 #if defined(CONFIG_DDR_32BIT)
75 /* set burst length to 8 for 32-bit data path */
76 /* DLL,normal,seq,4/2.5, 8 burst len */
77 #define CONFIG_SYS_DDR_MODE 0x00000023
79 /* the default burst length is 4 - for 64-bit data path */
80 /* DLL,normal,seq,4/2.5, 4 burst len */
81 #define CONFIG_SYS_DDR_MODE 0x00000022
86 * SDRAM on the Local Bus
88 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
89 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
92 * FLASH on the Local Bus
94 #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */
95 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
98 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
99 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
101 #undef CONFIG_SYS_FLASH_CHECKSUM
102 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
103 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
105 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
107 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
108 #define CONFIG_SYS_RAMBOOT
110 #undef CONFIG_SYS_RAMBOOT
113 #define CONFIG_SYS_INIT_RAM_LOCK 1
114 /* Initial RAM address */
115 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
116 /* Size of used area in RAM*/
117 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
119 #define CONFIG_SYS_GBL_DATA_OFFSET \
120 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
121 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
123 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
124 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
127 * Local Bus LCRR and LBCR regs
128 * LCRR: DLL bypass, Clock divider is 4
129 * External Local Bus rate is
130 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
132 #define CONFIG_SYS_LBC_LBCR 0x00000000
134 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
139 #define CONFIG_SYS_NS16550_SERIAL
140 #define CONFIG_SYS_NS16550_REG_SIZE 1
141 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
143 #define CONFIG_SYS_BAUDRATE_TABLE \
144 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
146 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
147 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
150 #define CONFIG_SYS_I2C
151 #define CONFIG_SYS_I2C_FSL
152 #define CONFIG_SYS_FSL_I2C_SPEED 400000
153 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
154 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
155 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
156 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
157 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
158 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69}, {1, 0x69} }
159 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
162 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
163 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
164 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
165 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
169 * Addresses are mapped 1-1.
171 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
172 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
173 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
174 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
175 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
176 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
177 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
178 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
179 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
181 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
182 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
183 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
184 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
185 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
186 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
187 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
188 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
189 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
191 #if defined(CONFIG_PCI)
193 #undef CONFIG_EEPRO100
196 #if !defined(CONFIG_PCI_PNP)
197 #define PCI_ENET0_IOADDR 0xFIXME
198 #define PCI_ENET0_MEMADDR 0xFIXME
199 #define PCI_IDSEL_NUMBER 0xFIXME
202 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
203 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
205 #endif /* CONFIG_PCI */
211 #if defined(CONFIG_TSEC_ENET)
213 #define CONFIG_TSEC1 1
214 #define CONFIG_TSEC1_NAME "TSEC0"
215 #define CONFIG_TSEC2 1
216 #define CONFIG_TSEC2_NAME "TSEC1"
217 #define CONFIG_PHY_BCM5421S 1
218 #define TSEC1_PHY_ADDR 0x19
219 #define TSEC2_PHY_ADDR 0x1a
220 #define TSEC1_PHYIDX 0
221 #define TSEC2_PHYIDX 0
222 #define TSEC1_FLAGS TSEC_GIGABIT
223 #define TSEC2_FLAGS TSEC_GIGABIT
225 /* Options are: TSEC[0-1] */
226 #define CONFIG_ETHPRIME "TSEC0"
228 #endif /* CONFIG_TSEC_ENET */
233 #ifndef CONFIG_SYS_RAMBOOT
234 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
235 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
236 #define CONFIG_ENV_SIZE 0x2000
238 /* Address and size of Redundant Environment Sector */
239 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
240 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
243 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
244 #define CONFIG_ENV_SIZE 0x2000
247 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
248 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
253 #define CONFIG_BOOTP_BOOTFILESIZE
256 * Command line configuration.
259 #undef CONFIG_WATCHDOG /* watchdog disabled */
262 * Miscellaneous configurable options
264 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
267 * For booting Linux, the board info and command line data
268 * have to be in the first 256 MB of memory, since this is
269 * the maximum mapped by the Linux kernel during initialization.
271 /* Initial Memory map for Linux*/
272 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
274 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
276 /* System IO Config */
277 #define CONFIG_SYS_SICRH 0
278 #define CONFIG_SYS_SICRL SICRL_LDP_A
281 #define CONFIG_PCI_INDIRECT_BRIDGE
284 #if defined(CONFIG_CMD_KGDB)
285 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
289 * Environment Configuration
291 #define CONFIG_ENV_OVERWRITE
293 #if defined(CONFIG_TSEC_ENET)
294 #define CONFIG_HAS_ETH0
295 #define CONFIG_HAS_ETH1
298 #define CONFIG_HOSTNAME "SBC8349"
299 #define CONFIG_ROOTPATH "/tftpboot/rootfs"
300 #define CONFIG_BOOTFILE "uImage"
302 /* default location for tftp and bootm */
303 #define CONFIG_LOADADDR 800000
305 #define CONFIG_EXTRA_ENV_SETTINGS \
307 "hostname=sbc8349\0" \
308 "nfsargs=setenv bootargs root=/dev/nfs rw " \
309 "nfsroot=${serverip}:${rootpath}\0" \
310 "ramargs=setenv bootargs root=/dev/ram rw\0" \
311 "addip=setenv bootargs ${bootargs} " \
312 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
313 ":${hostname}:${netdev}:off panic=1\0" \
314 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
315 "flash_nfs=run nfsargs addip addtty;" \
316 "bootm ${kernel_addr}\0" \
317 "flash_self=run ramargs addip addtty;" \
318 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
319 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
321 "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \
322 "update=protect off ff800000 ff83ffff; " \
323 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
324 "upd=run load update\0" \
326 "fdtfile=sbc8349.dtb\0" \
329 #define CONFIG_NFSBOOTCOMMAND \
330 "setenv bootargs root=/dev/nfs rw " \
331 "nfsroot=$serverip:$rootpath " \
332 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
334 "console=$consoledev,$baudrate $othbootargs;" \
335 "tftp $loadaddr $bootfile;" \
336 "tftp $fdtaddr $fdtfile;" \
337 "bootm $loadaddr - $fdtaddr"
339 #define CONFIG_RAMBOOTCOMMAND \
340 "setenv bootargs root=/dev/ram rw " \
341 "console=$consoledev,$baudrate $othbootargs;" \
342 "tftp $ramdiskaddr $ramdiskfile;" \
343 "tftp $loadaddr $bootfile;" \
344 "tftp $fdtaddr $fdtfile;" \
345 "bootm $loadaddr $ramdiskaddr $fdtaddr"
347 #define CONFIG_BOOTCOMMAND "run flash_self"
349 #endif /* __CONFIG_H */