1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * WindRiver SBC8349 U-Boot configuration file.
4 * Copyright (c) 2006, 2007 Wind River Systems, Inc.
6 * Paul Gortmaker <paul.gortmaker@windriver.com>
7 * Based on the MPC8349EMDS config.
11 * sbc8349 board configuration file.
18 * High Level Configuration Options
20 #define CONFIG_E300 1 /* E300 Family */
22 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
23 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
25 #define CONFIG_SYS_IMMR 0xE0000000
27 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
28 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
29 #define CONFIG_SYS_MEMTEST_END 0x00100000
34 #undef CONFIG_DDR_ECC /* only for ECC DDR module */
35 #undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
36 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
37 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */
40 * 32-bit data path mode.
42 * Please note that using this mode for devices with the real density of 64-bit
43 * effectively reduces the amount of available memory due to the effect of
44 * wrapping around while translating address to row/columns, for example in the
45 * 256MB module the upper 128MB get aliased with contents of the lower
46 * 128MB); normally this define should be used for devices with real 32-bit
49 #undef CONFIG_DDR_32BIT
51 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
52 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
53 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
54 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
55 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
56 #define CONFIG_DDR_2T_TIMING
58 #if defined(CONFIG_SPD_EEPROM)
60 * Determine DDR configuration from I2C interface.
62 #define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */
66 * Manually set up DDR parameters
67 * NB: manual DDR setup untested on sbc834x
69 #define CONFIG_SYS_DDR_SIZE 256 /* MB */
70 #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
71 | CSCONFIG_ROW_BIT_13 \
72 | CSCONFIG_COL_BIT_10)
73 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
74 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
75 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
76 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
78 #if defined(CONFIG_DDR_32BIT)
79 /* set burst length to 8 for 32-bit data path */
80 /* DLL,normal,seq,4/2.5, 8 burst len */
81 #define CONFIG_SYS_DDR_MODE 0x00000023
83 /* the default burst length is 4 - for 64-bit data path */
84 /* DLL,normal,seq,4/2.5, 4 burst len */
85 #define CONFIG_SYS_DDR_MODE 0x00000022
90 * SDRAM on the Local Bus
92 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
93 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
96 * FLASH on the Local Bus
98 #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */
99 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
102 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
103 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
105 #undef CONFIG_SYS_FLASH_CHECKSUM
106 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
107 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
109 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
111 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
112 #define CONFIG_SYS_RAMBOOT
114 #undef CONFIG_SYS_RAMBOOT
117 #define CONFIG_SYS_INIT_RAM_LOCK 1
118 /* Initial RAM address */
119 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
120 /* Size of used area in RAM*/
121 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
123 #define CONFIG_SYS_GBL_DATA_OFFSET \
124 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
125 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
127 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
128 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
131 * Local Bus LCRR and LBCR regs
132 * LCRR: DLL bypass, Clock divider is 4
133 * External Local Bus rate is
134 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
136 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
137 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
138 #define CONFIG_SYS_LBC_LBCR 0x00000000
140 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
145 #define CONFIG_SYS_NS16550_SERIAL
146 #define CONFIG_SYS_NS16550_REG_SIZE 1
147 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
149 #define CONFIG_SYS_BAUDRATE_TABLE \
150 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
152 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
153 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
156 #define CONFIG_SYS_I2C
157 #define CONFIG_SYS_I2C_FSL
158 #define CONFIG_SYS_FSL_I2C_SPEED 400000
159 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
160 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
161 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
162 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
163 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
164 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69}, {1, 0x69} }
165 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
168 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
169 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
170 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
171 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
175 * Addresses are mapped 1-1.
177 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
178 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
179 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
180 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
181 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
182 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
183 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
184 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
185 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
187 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
188 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
189 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
190 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
191 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
192 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
193 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
194 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
195 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
197 #if defined(CONFIG_PCI)
199 #undef CONFIG_EEPRO100
202 #if !defined(CONFIG_PCI_PNP)
203 #define PCI_ENET0_IOADDR 0xFIXME
204 #define PCI_ENET0_MEMADDR 0xFIXME
205 #define PCI_IDSEL_NUMBER 0xFIXME
208 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
209 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
211 #endif /* CONFIG_PCI */
217 #if defined(CONFIG_TSEC_ENET)
219 #define CONFIG_TSEC1 1
220 #define CONFIG_TSEC1_NAME "TSEC0"
221 #define CONFIG_TSEC2 1
222 #define CONFIG_TSEC2_NAME "TSEC1"
223 #define CONFIG_PHY_BCM5421S 1
224 #define TSEC1_PHY_ADDR 0x19
225 #define TSEC2_PHY_ADDR 0x1a
226 #define TSEC1_PHYIDX 0
227 #define TSEC2_PHYIDX 0
228 #define TSEC1_FLAGS TSEC_GIGABIT
229 #define TSEC2_FLAGS TSEC_GIGABIT
231 /* Options are: TSEC[0-1] */
232 #define CONFIG_ETHPRIME "TSEC0"
234 #endif /* CONFIG_TSEC_ENET */
239 #ifndef CONFIG_SYS_RAMBOOT
240 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
241 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
242 #define CONFIG_ENV_SIZE 0x2000
244 /* Address and size of Redundant Environment Sector */
245 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
246 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
249 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
250 #define CONFIG_ENV_SIZE 0x2000
253 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
254 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
259 #define CONFIG_BOOTP_BOOTFILESIZE
262 * Command line configuration.
265 #undef CONFIG_WATCHDOG /* watchdog disabled */
268 * Miscellaneous configurable options
270 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
273 * For booting Linux, the board info and command line data
274 * have to be in the first 256 MB of memory, since this is
275 * the maximum mapped by the Linux kernel during initialization.
277 /* Initial Memory map for Linux*/
278 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
280 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
282 /* System IO Config */
283 #define CONFIG_SYS_SICRH 0
284 #define CONFIG_SYS_SICRL SICRL_LDP_A
287 #define CONFIG_PCI_INDIRECT_BRIDGE
290 #if defined(CONFIG_CMD_KGDB)
291 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
295 * Environment Configuration
297 #define CONFIG_ENV_OVERWRITE
299 #if defined(CONFIG_TSEC_ENET)
300 #define CONFIG_HAS_ETH0
301 #define CONFIG_HAS_ETH1
304 #define CONFIG_HOSTNAME "SBC8349"
305 #define CONFIG_ROOTPATH "/tftpboot/rootfs"
306 #define CONFIG_BOOTFILE "uImage"
308 /* default location for tftp and bootm */
309 #define CONFIG_LOADADDR 800000
311 #define CONFIG_EXTRA_ENV_SETTINGS \
313 "hostname=sbc8349\0" \
314 "nfsargs=setenv bootargs root=/dev/nfs rw " \
315 "nfsroot=${serverip}:${rootpath}\0" \
316 "ramargs=setenv bootargs root=/dev/ram rw\0" \
317 "addip=setenv bootargs ${bootargs} " \
318 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
319 ":${hostname}:${netdev}:off panic=1\0" \
320 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
321 "flash_nfs=run nfsargs addip addtty;" \
322 "bootm ${kernel_addr}\0" \
323 "flash_self=run ramargs addip addtty;" \
324 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
325 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
327 "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \
328 "update=protect off ff800000 ff83ffff; " \
329 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
330 "upd=run load update\0" \
332 "fdtfile=sbc8349.dtb\0" \
335 #define CONFIG_NFSBOOTCOMMAND \
336 "setenv bootargs root=/dev/nfs rw " \
337 "nfsroot=$serverip:$rootpath " \
338 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
340 "console=$consoledev,$baudrate $othbootargs;" \
341 "tftp $loadaddr $bootfile;" \
342 "tftp $fdtaddr $fdtfile;" \
343 "bootm $loadaddr - $fdtaddr"
345 #define CONFIG_RAMBOOTCOMMAND \
346 "setenv bootargs root=/dev/ram rw " \
347 "console=$consoledev,$baudrate $othbootargs;" \
348 "tftp $ramdiskaddr $ramdiskfile;" \
349 "tftp $loadaddr $bootfile;" \
350 "tftp $fdtaddr $fdtfile;" \
351 "bootm $loadaddr $ramdiskaddr $fdtaddr"
353 #define CONFIG_BOOTCOMMAND "run flash_self"
355 #endif /* __CONFIG_H */