include/configs/sbc8349.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * WindRiver SBC8349 U-Boot configuration file.
   4  * Copyright (c) 2006, 2007 Wind River Systems, Inc.
   5  *
   6  * Paul Gortmaker <paul.gortmaker@windriver.com>
   7  * Based on the MPC8349EMDS config.
   8  */
   9
  10 /*
  11  * sbc8349 board configuration file.
  12  */
  13
  14 #ifndef __CONFIG_H
  15 #define __CONFIG_H
  16
  17 /*
  18  * High Level Configuration Options
  19  */
  20 #define CONFIG_E300             1       /* E300 Family */
  21 #define CONFIG_MPC834x          1       /* MPC834x family */
  22 #define CONFIG_MPC8349          1       /* MPC8349 specific */
  23
  24 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
  25 #undef CONFIG_MPC83XX_PCI2              /* support for 2nd PCI controller */
  26
  27 /*
  28  * The default if PCI isn't enabled, or if no PCI clk setting is given
  29  * is 66MHz; this is what the board defaults to when the PCI slot is
  30  * physically empty.  The board will automatically (i.e w/o jumpers)
  31  * clock down to 33MHz if you insert a 33MHz PCI card.
  32  */
  33 #ifdef CONFIG_PCI_33M
  34 #define CONFIG_83XX_CLKIN       33000000        /* in Hz */
  35 #else   /* 66M */
  36 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
  37 #endif
  38
  39 #ifndef CONFIG_SYS_CLK_FREQ
  40 #ifdef CONFIG_PCI_33M
  41 #define CONFIG_SYS_CLK_FREQ     33000000
  42 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_8X1
  43 #else   /* 66M */
  44 #define CONFIG_SYS_CLK_FREQ     66000000
  45 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_4X1
  46 #endif
  47 #endif
  48
  49 #define CONFIG_SYS_IMMR         0xE0000000
  50
  51 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  52 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  53 #define CONFIG_SYS_MEMTEST_END          0x00100000
  54
  55 /*
  56  * DDR Setup
  57  */
  58 #undef CONFIG_DDR_ECC                   /* only for ECC DDR module */
  59 #undef CONFIG_DDR_ECC_CMD               /* use DDR ECC user commands */
  60 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
  61 #define CONFIG_SYS_83XX_DDR_USES_CS0    /* WRS; Fsl board uses CS2/CS3 */
  62
  63 /*
  64  * 32-bit data path mode.
  65  *
  66  * Please note that using this mode for devices with the real density of 64-bit
  67  * effectively reduces the amount of available memory due to the effect of
  68  * wrapping around while translating address to row/columns, for example in the
  69  * 256MB module the upper 128MB get aliased with contents of the lower
  70  * 128MB); normally this define should be used for devices with real 32-bit
  71  * data path.
  72  */
  73 #undef CONFIG_DDR_32BIT
  74
  75 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
  76 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  77 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  78 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  79                                 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  80 #define CONFIG_DDR_2T_TIMING
  81
  82 #if defined(CONFIG_SPD_EEPROM)
  83 /*
  84  * Determine DDR configuration from I2C interface.
  85  */
  86 #define SPD_EEPROM_ADDRESS      0x52            /* DDR DIMM */
  87
  88 #else
  89 /*
  90  * Manually set up DDR parameters
  91  * NB: manual DDR setup untested on sbc834x
  92  */
  93 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
  94 #define CONFIG_SYS_DDR_CS2_CONFIG       (CSCONFIG_EN \
  95                                         | CSCONFIG_ROW_BIT_13 \
  96                                         | CSCONFIG_COL_BIT_10)
  97 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
  98 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
  99 #define CONFIG_SYS_DDR_CONTROL  0xc2000000      /* unbuffered,no DYN_PWR */
 100 #define CONFIG_SYS_DDR_INTERVAL 0x04060100      /* autocharge,no open page */
 101
 102 #if defined(CONFIG_DDR_32BIT)
 103 /* set burst length to 8 for 32-bit data path */
 104                                 /* DLL,normal,seq,4/2.5, 8 burst len */
 105 #define CONFIG_SYS_DDR_MODE     0x00000023
 106 #else
 107 /* the default burst length is 4 - for 64-bit data path */
 108                                 /* DLL,normal,seq,4/2.5, 4 burst len */
 109 #define CONFIG_SYS_DDR_MODE     0x00000022
 110 #endif
 111 #endif
 112
 113 /*
 114  * SDRAM on the Local Bus
 115  */
 116 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* Localbus SDRAM */
 117 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 118
 119 /*
 120  * FLASH on the Local Bus
 121  */
 122 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 123 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 124 #define CONFIG_SYS_FLASH_BASE           0xFF800000      /* start of FLASH   */
 125 #define CONFIG_SYS_FLASH_SIZE           8               /* flash size in MB */
 126 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 127
 128 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE \
 129                                         | BR_PS_16      /* 16 bit port */ \
 130                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 131                                         | BR_V)         /* valid */
 132
 133 #define CONFIG_SYS_OR0_PRELIM           (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 134                                         | OR_GPCM_XAM \
 135                                         | OR_GPCM_CSNT \
 136                                         | OR_GPCM_ACS_DIV2 \
 137                                         | OR_GPCM_XACS \
 138                                         | OR_GPCM_SCY_15 \
 139                                         | OR_GPCM_TRLX_SET \
 140                                         | OR_GPCM_EHTR_SET \
 141                                         | OR_GPCM_EAD)
 142                                         /* 0xFF806FF7 */
 143
 144                                         /* window base at flash base */
 145 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 146 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
 147
 148 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 149 #define CONFIG_SYS_MAX_FLASH_SECT       64      /* sectors per device */
 150
 151 #undef CONFIG_SYS_FLASH_CHECKSUM
 152 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 153 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 154
 155 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 156
 157 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 158 #define CONFIG_SYS_RAMBOOT
 159 #else
 160 #undef  CONFIG_SYS_RAMBOOT
 161 #endif
 162
 163 #define CONFIG_SYS_INIT_RAM_LOCK        1
 164                                         /* Initial RAM address */
 165 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000
 166                                         /* Size of used area in RAM*/
 167 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000
 168
 169 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 170                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 171 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 172
 173 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024)    /* Reserve 256 kB for Mon */
 174 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 175
 176 /*
 177  * Local Bus LCRR and LBCR regs
 178  *    LCRR:  DLL bypass, Clock divider is 4
 179  * External Local Bus rate is
 180  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 181  */
 182 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 183 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 184 #define CONFIG_SYS_LBC_LBCR     0x00000000
 185
 186 #undef CONFIG_SYS_LB_SDRAM      /* if board has SDRAM on local bus */
 187
 188 #ifdef CONFIG_SYS_LB_SDRAM
 189 /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/
 190 /*
 191  * Base Register 2 and Option Register 2 configure SDRAM.
 192  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 193  *
 194  * For BR2, need:
 195  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 196  *    port-size = 32-bits = BR2[19:20] = 11
 197  *    no parity checking = BR2[21:22] = 00
 198  *    SDRAM for MSEL = BR2[24:26] = 011
 199  *    Valid = BR[31] = 1
 200  *
 201  * 0    4    8    12   16   20   24   28
 202  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
 203  */
 204
 205 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_LBC_SDRAM_BASE \
 206                                         | BR_PS_32 \
 207                                         | BR_MS_SDRAM \
 208                                         | BR_V)
 209                                         /* 0xF0001861 */
 210 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_LBC_SDRAM_BASE
 211 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_64MB)
 212
 213 /*
 214  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 215  *
 216  * For OR2, need:
 217  *    64MB mask for AM, OR2[0:7] = 1111 1100
 218  *                 XAM, OR2[17:18] = 11
 219  *    9 columns OR2[19-21] = 010
 220  *    13 rows   OR2[23-25] = 100
 221  *    EAD set for extra time OR[31] = 1
 222  *
 223  * 0    4    8    12   16   20   24   28
 224  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
 225  */
 226
 227 #define CONFIG_SYS_OR2_PRELIM   (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
 228                         | OR_SDRAM_XAM \
 229                         | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
 230                         | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
 231                         | OR_SDRAM_EAD)
 232                         /* 0xFC006901 */
 233
 234                                 /* LB sdram refresh timer, about 6us */
 235 #define CONFIG_SYS_LBC_LSRT     0x32000000
 236                                 /* LB refresh timer prescal, 266MHz/32 */
 237 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 238
 239 #define CONFIG_SYS_LBC_LSDMR_COMMON     (LSDMR_RFEN \
 240                                         | LSDMR_BSMA1516 \
 241                                         | LSDMR_RFCR8 \
 242                                         | LSDMR_PRETOACT6 \
 243                                         | LSDMR_ACTTORW3 \
 244                                         | LSDMR_BL8 \
 245                                         | LSDMR_WRC3 \
 246                                         | LSDMR_CL3)
 247
 248 /*
 249  * SDRAM Controller configuration sequence.
 250  */
 251 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 252 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 253 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 254 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 255 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 256 #endif
 257
 258 /*
 259  * Serial Port
 260  */
 261 #define CONFIG_SYS_NS16550_SERIAL
 262 #define CONFIG_SYS_NS16550_REG_SIZE    1
 263 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 264
 265 #define CONFIG_SYS_BAUDRATE_TABLE  \
 266                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 267
 268 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 269 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 270
 271 /* I2C */
 272 #define CONFIG_SYS_I2C
 273 #define CONFIG_SYS_I2C_FSL
 274 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 275 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 276 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 277 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 278 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 279 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 280 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69}, {1, 0x69} }
 281 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
 282
 283 /* TSEC */
 284 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 285 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 286 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 287 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 288
 289 /*
 290  * General PCI
 291  * Addresses are mapped 1-1.
 292  */
 293 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 294 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 295 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 296 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 297 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 298 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 299 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 300 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 301 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 302
 303 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 304 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 305 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 306 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 307 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 308 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 309 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 310 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 311 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 312
 313 #if defined(CONFIG_PCI)
 314
 315 #define PCI_64BIT
 316 #define PCI_ONE_PCI1
 317 #if defined(PCI_64BIT)
 318 #undef PCI_ALL_PCI1
 319 #undef PCI_TWO_PCI1
 320 #undef PCI_ONE_PCI1
 321 #endif
 322
 323 #undef CONFIG_EEPRO100
 324 #undef CONFIG_TULIP
 325
 326 #if !defined(CONFIG_PCI_PNP)
 327         #define PCI_ENET0_IOADDR        0xFIXME
 328         #define PCI_ENET0_MEMADDR       0xFIXME
 329         #define PCI_IDSEL_NUMBER        0xFIXME
 330 #endif
 331
 332 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 333 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 334
 335 #endif  /* CONFIG_PCI */
 336
 337 /*
 338  * TSEC configuration
 339  */
 340
 341 #if defined(CONFIG_TSEC_ENET)
 342
 343 #define CONFIG_TSEC1    1
 344 #define CONFIG_TSEC1_NAME       "TSEC0"
 345 #define CONFIG_TSEC2    1
 346 #define CONFIG_TSEC2_NAME       "TSEC1"
 347 #define CONFIG_PHY_BCM5421S     1
 348 #define TSEC1_PHY_ADDR          0x19
 349 #define TSEC2_PHY_ADDR          0x1a
 350 #define TSEC1_PHYIDX            0
 351 #define TSEC2_PHYIDX            0
 352 #define TSEC1_FLAGS             TSEC_GIGABIT
 353 #define TSEC2_FLAGS             TSEC_GIGABIT
 354
 355 /* Options are: TSEC[0-1] */
 356 #define CONFIG_ETHPRIME         "TSEC0"
 357
 358 #endif  /* CONFIG_TSEC_ENET */
 359
 360 /*
 361  * Environment
 362  */
 363 #ifndef CONFIG_SYS_RAMBOOT
 364         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 365         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 366         #define CONFIG_ENV_SIZE         0x2000
 367
 368 /* Address and size of Redundant Environment Sector     */
 369 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 370 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 371
 372 #else
 373         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 374         #define CONFIG_ENV_SIZE         0x2000
 375 #endif
 376
 377 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 378 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 379
 380 /*
 381  * BOOTP options
 382  */
 383 #define CONFIG_BOOTP_BOOTFILESIZE
 384
 385 /*
 386  * Command line configuration.
 387  */
 388
 389 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 390
 391 /*
 392  * Miscellaneous configurable options
 393  */
 394 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 395
 396 /*
 397  * For booting Linux, the board info and command line data
 398  * have to be in the first 256 MB of memory, since this is
 399  * the maximum mapped by the Linux kernel during initialization.
 400  */
 401                                 /* Initial Memory map for Linux*/
 402 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 403
 404 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 405
 406 #if 1 /*528/264*/
 407 #define CONFIG_SYS_HRCW_LOW (\
 408         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 409         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 410         HRCWL_CSB_TO_CLKIN |\
 411         HRCWL_VCO_1X2 |\
 412         HRCWL_CORE_TO_CSB_2X1)
 413 #elif 0 /*396/132*/
 414 #define CONFIG_SYS_HRCW_LOW (\
 415         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 416         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 417         HRCWL_CSB_TO_CLKIN |\
 418         HRCWL_VCO_1X4 |\
 419         HRCWL_CORE_TO_CSB_3X1)
 420 #elif 0 /*264/132*/
 421 #define CONFIG_SYS_HRCW_LOW (\
 422         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 423         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 424         HRCWL_CSB_TO_CLKIN |\
 425         HRCWL_VCO_1X4 |\
 426         HRCWL_CORE_TO_CSB_2X1)
 427 #elif 0 /*132/132*/
 428 #define CONFIG_SYS_HRCW_LOW (\
 429         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 430         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 431         HRCWL_CSB_TO_CLKIN |\
 432         HRCWL_VCO_1X4 |\
 433         HRCWL_CORE_TO_CSB_1X1)
 434 #elif 0 /*264/264 */
 435 #define CONFIG_SYS_HRCW_LOW (\
 436         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 437         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 438         HRCWL_CSB_TO_CLKIN |\
 439         HRCWL_VCO_1X4 |\
 440         HRCWL_CORE_TO_CSB_1X1)
 441 #endif
 442
 443 #if defined(PCI_64BIT)
 444 #define CONFIG_SYS_HRCW_HIGH (\
 445         HRCWH_PCI_HOST |\
 446         HRCWH_64_BIT_PCI |\
 447         HRCWH_PCI1_ARBITER_ENABLE |\
 448         HRCWH_PCI2_ARBITER_DISABLE |\
 449         HRCWH_CORE_ENABLE |\
 450         HRCWH_FROM_0X00000100 |\
 451         HRCWH_BOOTSEQ_DISABLE |\
 452         HRCWH_SW_WATCHDOG_DISABLE |\
 453         HRCWH_ROM_LOC_LOCAL_16BIT |\
 454         HRCWH_TSEC1M_IN_GMII |\
 455         HRCWH_TSEC2M_IN_GMII)
 456 #else
 457 #define CONFIG_SYS_HRCW_HIGH (\
 458         HRCWH_PCI_HOST |\
 459         HRCWH_32_BIT_PCI |\
 460         HRCWH_PCI1_ARBITER_ENABLE |\
 461         HRCWH_PCI2_ARBITER_ENABLE |\
 462         HRCWH_CORE_ENABLE |\
 463         HRCWH_FROM_0X00000100 |\
 464         HRCWH_BOOTSEQ_DISABLE |\
 465         HRCWH_SW_WATCHDOG_DISABLE |\
 466         HRCWH_ROM_LOC_LOCAL_16BIT |\
 467         HRCWH_TSEC1M_IN_GMII |\
 468         HRCWH_TSEC2M_IN_GMII)
 469 #endif
 470
 471 /* System IO Config */
 472 #define CONFIG_SYS_SICRH 0
 473 #define CONFIG_SYS_SICRL SICRL_LDP_A
 474
 475 #define CONFIG_SYS_HID0_INIT    0x000000000
 476 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK \
 477                                 | HID0_ENABLE_INSTRUCTION_CACHE)
 478
 479 /* #define CONFIG_SYS_HID0_FINAL        (\
 480         HID0_ENABLE_INSTRUCTION_CACHE |\
 481         HID0_ENABLE_M_BIT |\
 482         HID0_ENABLE_ADDRESS_BROADCAST) */
 483
 484 #define CONFIG_SYS_HID2 HID2_HBE
 485
 486 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 487
 488 /* DDR @ 0x00000000 */
 489 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 490                                 | BATL_PP_RW \
 491                                 | BATL_MEMCOHERENCE)
 492 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 493                                 | BATU_BL_256M \
 494                                 | BATU_VS \
 495                                 | BATU_VP)
 496
 497 /* PCI @ 0x80000000 */
 498 #ifdef CONFIG_PCI
 499 #define CONFIG_PCI_INDIRECT_BRIDGE
 500 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE \
 501                                 | BATL_PP_RW \
 502                                 | BATL_MEMCOHERENCE)
 503 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 504                                 | BATU_BL_256M \
 505                                 | BATU_VS \
 506                                 | BATU_VP)
 507 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 508                                 | BATL_PP_RW \
 509                                 | BATL_CACHEINHIBIT \
 510                                 | BATL_GUARDEDSTORAGE)
 511 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 512                                 | BATU_BL_256M \
 513                                 | BATU_VS \
 514                                 | BATU_VP)
 515 #else
 516 #define CONFIG_SYS_IBAT1L       (0)
 517 #define CONFIG_SYS_IBAT1U       (0)
 518 #define CONFIG_SYS_IBAT2L       (0)
 519 #define CONFIG_SYS_IBAT2U       (0)
 520 #endif
 521
 522 #ifdef CONFIG_MPC83XX_PCI2
 523 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE \
 524                                 | BATL_PP_RW \
 525                                 | BATL_MEMCOHERENCE)
 526 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE \
 527                                 | BATU_BL_256M \
 528                                 | BATU_VS \
 529                                 | BATU_VP)
 530 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE \
 531                                 | BATL_PP_RW \
 532                                 | BATL_CACHEINHIBIT \
 533                                 | BATL_GUARDEDSTORAGE)
 534 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE \
 535                                 | BATU_BL_256M \
 536                                 | BATU_VS \
 537                                 | BATU_VP)
 538 #else
 539 #define CONFIG_SYS_IBAT3L       (0)
 540 #define CONFIG_SYS_IBAT3U       (0)
 541 #define CONFIG_SYS_IBAT4L       (0)
 542 #define CONFIG_SYS_IBAT4U       (0)
 543 #endif
 544
 545 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
 546 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 547                                 | BATL_PP_RW \
 548                                 | BATL_CACHEINHIBIT \
 549                                 | BATL_GUARDEDSTORAGE)
 550 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 551                                 | BATU_BL_256M \
 552                                 | BATU_VS \
 553                                 | BATU_VP)
 554
 555 /* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 556 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_LBC_SDRAM_BASE \
 557                                 | BATL_PP_RW \
 558                                 | BATL_MEMCOHERENCE \
 559                                 | BATL_GUARDEDSTORAGE)
 560 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_LBC_SDRAM_BASE \
 561                                 | BATU_BL_256M \
 562                                 | BATU_VS \
 563                                 | BATU_VP)
 564
 565 #define CONFIG_SYS_IBAT7L       (0)
 566 #define CONFIG_SYS_IBAT7U       (0)
 567
 568 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 569 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 570 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 571 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 572 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 573 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 574 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 575 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 576 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 577 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 578 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 579 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 580 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 581 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 582 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 583 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 584
 585 #if defined(CONFIG_CMD_KGDB)
 586 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 587 #endif
 588
 589 /*
 590  * Environment Configuration
 591  */
 592 #define CONFIG_ENV_OVERWRITE
 593
 594 #if defined(CONFIG_TSEC_ENET)
 595 #define CONFIG_HAS_ETH0
 596 #define CONFIG_HAS_ETH1
 597 #endif
 598
 599 #define CONFIG_HOSTNAME         "SBC8349"
 600 #define CONFIG_ROOTPATH         "/tftpboot/rootfs"
 601 #define CONFIG_BOOTFILE         "uImage"
 602
 603                                 /* default location for tftp and bootm */
 604 #define CONFIG_LOADADDR         800000
 605
 606 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 607         "netdev=eth0\0"                                                 \
 608         "hostname=sbc8349\0"                                            \
 609         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 610                 "nfsroot=${serverip}:${rootpath}\0"                     \
 611         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 612         "addip=setenv bootargs ${bootargs} "                            \
 613                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 614                 ":${hostname}:${netdev}:off panic=1\0"                  \
 615         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 616         "flash_nfs=run nfsargs addip addtty;"                           \
 617                 "bootm ${kernel_addr}\0"                                \
 618         "flash_self=run ramargs addip addtty;"                          \
 619                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 620         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 621                 "bootm\0"                                               \
 622         "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0"               \
 623         "update=protect off ff800000 ff83ffff; "                        \
 624                 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
 625         "upd=run load update\0"                                         \
 626         "fdtaddr=780000\0"                                              \
 627         "fdtfile=sbc8349.dtb\0"                                         \
 628         ""
 629
 630 #define CONFIG_NFSBOOTCOMMAND                                           \
 631         "setenv bootargs root=/dev/nfs rw "                             \
 632                 "nfsroot=$serverip:$rootpath "                          \
 633                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 634                                                         "$netdev:off "  \
 635                 "console=$consoledev,$baudrate $othbootargs;"           \
 636         "tftp $loadaddr $bootfile;"                                     \
 637         "tftp $fdtaddr $fdtfile;"                                       \
 638         "bootm $loadaddr - $fdtaddr"
 639
 640 #define CONFIG_RAMBOOTCOMMAND                                           \
 641         "setenv bootargs root=/dev/ram rw "                             \
 642                 "console=$consoledev,$baudrate $othbootargs;"           \
 643         "tftp $ramdiskaddr $ramdiskfile;"                               \
 644         "tftp $loadaddr $bootfile;"                                     \
 645         "tftp $fdtaddr $fdtfile;"                                       \
 646         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 647
 648 #define CONFIG_BOOTCOMMAND      "run flash_self"
 649
 650 #endif  /* __CONFIG_H */