include/configs/sama5d4ek.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuration settings for the SAMA5D4EK board.
   4  *
   5  * Copyright (C) 2014 Atmel
   6  *                    Bo Shen <voice.shen@atmel.com>
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #include "at91-sama5_common.h"
  13
  14 /* SDRAM */
  15 #define CONFIG_SYS_SDRAM_BASE           0x20000000
  16 #define CONFIG_SYS_SDRAM_SIZE           0x20000000
  17
  18 #ifdef CONFIG_SPL_BUILD
  19 #define CONFIG_SYS_INIT_SP_ADDR         0x218000
  20 #else
  21 #define CONFIG_SYS_INIT_SP_ADDR \
  22         (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
  23 #endif
  24
  25 #define CONFIG_SYS_LOAD_ADDR            0x22000000 /* load address */
  26
  27 #ifdef CONFIG_CMD_SF
  28 #define CONFIG_SF_DEFAULT_SPEED         30000000
  29 #endif
  30
  31 /* NAND flash */
  32 #ifdef CONFIG_CMD_NAND
  33 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  34 #define CONFIG_SYS_NAND_BASE            0x80000000
  35 /* our ALE is AD21 */
  36 #define CONFIG_SYS_NAND_MASK_ALE        (1 << 21)
  37 /* our CLE is AD22 */
  38 #define CONFIG_SYS_NAND_MASK_CLE        (1 << 22)
  39 #define CONFIG_SYS_NAND_ONFI_DETECTION
  40 /* PMECC & PMERRLOC */
  41 #define CONFIG_ATMEL_NAND_HWECC
  42 #define CONFIG_ATMEL_NAND_HW_PMECC
  43 #endif
  44
  45 /* SPL */
  46 #define CONFIG_SPL_TEXT_BASE            0x200000
  47 #define CONFIG_SPL_MAX_SIZE             0x18000
  48 #define CONFIG_SPL_BSS_START_ADDR       0x20000000
  49 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  50 #define CONFIG_SYS_SPL_MALLOC_START     0x20080000
  51 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x80000
  52
  53 #define CONFIG_SYS_MONITOR_LEN          (512 << 10)
  54
  55 #ifdef CONFIG_SD_BOOT
  56 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
  57 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.img"
  58
  59 #elif CONFIG_SPI_BOOT
  60 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x10000
  61
  62 #elif CONFIG_NAND_BOOT
  63 #define CONFIG_SPL_NAND_DRIVERS
  64 #define CONFIG_SPL_NAND_BASE
  65 #endif
  66 #define CONFIG_PMECC_CAP                8
  67 #define CONFIG_PMECC_SECTOR_SIZE        512
  68 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
  69 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  70 #define CONFIG_SYS_NAND_PAGE_SIZE       0x1000
  71 #define CONFIG_SYS_NAND_PAGE_COUNT      64
  72 #define CONFIG_SYS_NAND_OOBSIZE         224
  73 #define CONFIG_SYS_NAND_BLOCK_SIZE      0x40000
  74 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0x0
  75 #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
  76
  77 #endif